capacitance modelling by a nmos

Avanti Hspice:
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I am trying to model a 45 pf capacitance(verified this by dumping
caps) by a nmos( drain, source, bulk shorted to gnd), the 2 terminals
of the capacitor
being the gate and ground. Pretty huge one 20u/6u*100
M11 vss cap vss vss nch w=20u l=6u m=100

However when I run a tran analysis that pumps current into this cap, I
see that
the voltage at the gate node rises too slowly. current flowing in is
~4.5uA.

Expected Voltage rise rate = It/C = (4.5/45)V/us
Rises at around 0.01 volt per 20us in the simulation.

Anything wrong here. Or shoul dI be doing anything extra in the
testbench.
Am I missing something.

Thanks a lot
-Dinakaran

 

I am able to remove thsi error when I run the tran analysis with 1ns
as the timestep instead of 0.1ns that I used below in the analysis
below. The nmos-capacitor shows the desired voltage increase rate.

I dont understand this at all. Why should this be the case?
Thanks
-Dinakaran