Can cadence do VHDL?

Hi,

Sorry to ask such a basic question, but the documentation on-site is not very
clear on something this general. I know Cadence includes a verilog compiler
and related synthesis tools, but does it have a VHDL compiler and related tools?

I just need to know what (if any) they are called etc.

 

Normally somebody at your side should be able to answer
this question.

In general yes Cadence has tools for VHDL.
The simulator is called NCSIM and the synthesis tool
does not care about which HDL to synthesise.
This is true for I think all commercial synthesis tools

For more basic info follow think link:
http://www.cadence.com/products/functional_ver/index.aspx

Bernd

 

I could have tried google I guess.

It seems to simulate the library which would be produced by a compiler: would
you know what the VHDL compiler is? I recall 'icds' can load VHDL files as
designs... as you can tell I don't know what THE tool to use is. There is a
'verilog' that can compile VErilog source files, what is the equivalent for
VHDL (if any)?

 

There are two options the first one is the IUS suite I pointed to you.
I'm not an expert for digital, but the tools consists of an elaborator,
compiler and simulator. I think bundled in a command called 'ncsim'.

The second option is what you called 'icds' the Cadence Design Framework
it is more a tool for doing analog design, but the is a HDL simulator
'Verilog-XL' included and the is a 'VHDL Toolbox'.

Sorry I don't have more detailed information because we are doing strict
Verilog at our side and your first question seems to me
more general.

Bernd

 

The compilation is done with "ncvhdl" (as opposed to "ncvlog"), and then
elaboration with "ncelab", and simulation with "ncsim".

In (much) older releases there was the leapfrog simulation, which used cv to
compile the vhdl. Vhdl-in in DFII still uses cv to do its compilation
(unfortunately) in order to be able to parse the VHDL code.

Regards,

Andrew.

 

Thanks for everyone's response. One further question: is it possible to
run a simulation with input taken from standard input (a pipe) or a named
pipe (FIFO in file system)? I was able to do the latter with another simulator,
but it seems 'ncsim' will not do either. (These are running on a Solaris host.)

For example, endfile(input) seems to always return true (event before any
input is read). Using a FIFO, endfile() is interrupted with a file I/O error
that the file cannot be opened for reading (it looks like the end of file is
reached but it is not processing this fact).

The original input files will be too big to fit in my allotted disk space, so
this is a major problem (using pipe/FIFO allows them to be uncompressed on the
fly).