Calibre question: why initial ports before transformation differ from netlist IO subckt ports

Discussion in 'Cadence' started by vlsidesign, Nov 18, 2006.

  1. vlsidesign

    vlsidesign Guest

    I was noticing in my calibre lvs report the initial port count before
    transformation was 1194 for the source (netlist from schematic), and
    then after transformation it was 1192 (which matches layout).

    However, when I parsed the source (cdl created from schematic) and
    counted the IO pins defined in SUBCKT (toplevel), it only had 1192.

    Wondering if anyone else noticed this happening before and why this
    might happen?
     
    vlsidesign, Nov 18, 2006
    #1
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