Cadence LVS error

Discussion in 'Cadence' started by pallavi, Oct 5, 2007.

  1. pallavi

    pallavi Guest

    Hi,

    I am getting an error while running the LVS in Cadence. The error
    message says: The inv schematic has changed after it was last
    extracted. si: the netlist did not complete successfully.

    I had completed a sucessful LVS check on this schematic some time ago.
    No suddenly I see this error. I have not modified any schematics/
    layout/ extracted layout.

    This error is not limited to onr schematic but all the schematics
    present in my library. I am not sure how to resolve this issue.

    Can someone please hyelp me find solution for this problem? Any help
    is really appreciated.

    Thank you,
    Pallavi
     
    pallavi, Oct 5, 2007
    #1
  2. pallavi

    The Master Guest

    The only times I have seen that, the "solution" is to open the schematic
    and do a "check and save" on it. Further in your post, you mention that
    you made no schematic edits, so I have no idea why the schematics would
    suddenly need to have this done again. Did you by chance replace, or
    rename a reference library?

    I would recomend trying to run LVS on a very small simple schematic, and
    see if the "check and save" works... If it does, then I have no idea what
    would have caused your entire library to mess up like that.
     
    The Master, Oct 5, 2007
    #2
  3. pallavi

    pallavi Guest


    thanks for replying. I will try 'check and save' option.
    I did not change the library name. How do I make sure my entire
    library is not messed up? Is there a way to verify that?

    If the layout (eg. for a simple Inverter) is 'Flattened', will that
    cause this error?

    -Pallavi
     
    pallavi, Oct 5, 2007
    #3
  4. pallavi

    Mobil Guest

    'Flatten' won't cause this error. Just click 'save and check' option.
     
    Mobil, Oct 7, 2007
    #4
  5. pallavi

    The Master Guest

    Yes. The "check and save" is on the schematic side. It doesn't matter if
    the layout view is used or not, what matters is that the schematic is
    used...

    I don't know if there is a skill or menu function to do a "check and save"
    on all schematic views. If there isn't, the only way is to do it manually
    cell by cell.
     
    The Master, Oct 7, 2007
    #5
  6. pallavi

    pallavi Guest

    Hi,

    Check and Save option did not help in fixing this issue. It is
    something else.
    Is there a way I can track timestap on the schematics? That may help
    me find what schematic it is referring to during LVS check.
     
    pallavi, Oct 8, 2007
    #6
  7. pallavi

    S. Badel Guest

    I am getting an error while running the LVS in Cadence. The error
    Is 'inv' your top cell ? It might be due to a change in a child cell, that would explain why the
    error happens with different designs. You can do a hierarchical check/save by choosing
    check->hierarchy in the schematic editor.

    Or, it might be the switch/stop view list. Check the content of your .simrc file (or post it)


    Cheers,
    Stéphane
     
    S. Badel, Oct 9, 2007
    #7
  8. pallavi

    The Master Guest

    Ug... In that case I have no idea what is wrong. Like I said, every time
    I have ever seen that error, it was a check and save problem of some
    sort... It's weird that it didn't help.

    Has anyone ever seen that error in cases that didn't apply to "check and
    save"?
     
    The Master, Oct 9, 2007
    #8
  9. pallavi

    S. Badel Guest

    Has anyone ever seen that error in cases that didn't apply to "check and
    Yes : when the netlister ends up with a non-schematic/extracted view which is not in the stop view list.

    It figures this must be a schematic of some sort, but since it's lacking the lastSchematicExtraction
    property, it throws this error.

    Stéphane
     
    S. Badel, Oct 9, 2007
    #9
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