bus pin paranth. conversion problem in .v to sch. utility

Thank you TTT, Thank you Andrew for responses.
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Dear Andrew,
1. I am trying to usenet news. I hope to strike it correct.
2. I found out the way to map the names in Assura, dint give a try any
way. BIND NETS option in Assura LVS.
3. Further to the same situation i am trying to write a skill code.
for which i have posted a message to the group dt.5th may 2004. Could
you give a suggestion how to modify the pin property in VLE from skill
code.
Regards,
Aravind

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Yes. Your assumption is right. It is possible to map the names in
Assura
(at least I think so) as an alternative.

I've not seen the question on comp.cad.cadence yet (I don't monitor it
all
the time, and it takes a while to propagate with usenet news).

Andrew.

On Apr 29, 7:40pm, Aravind Karanth V wrote:
Subject: Re: bus pin naming conversion problem in .v to sch.

Dear Andrew,

Thank you very much.
Yup, I posted the same message to the group.

But this kind of conversion is leading me to LVS errors in assura.
So by your mail i understand that my layout also needs to have same
bus
naming convention as schematic. i.e. < > naming in layout too.
I hope my assumption is right !

Regards,
Aravind Karanth V.
---------------------------
Andrew Beckett wrote:

Aravind,

Really you'd be best to contact customer support rather than me
directly, but I can answer this quickly.

<> are DFII's syntax for busses - the database knows that this is the
bus
syntax, and it knows how to manipulate busses that way.

So it is correct for these to be translated during verilog-in.

When you netlist to Verilog again, they will be converted back to [].

[] would _not_ be interpreted as a bus in DFII, so you don't really
want
them to be kept as []; it would have to split all bus pins up to
individual pins if this were the case (because it would see a[10:0] as
a
single bit wire instead of an 11 bit bus, otherwise).

Regards,

Andrew.

On Apr 29, 7:28pm, Aravind Karanth V wrote:
Subject: bus pin naming conversion problem in .v to sch.

Dear Andrew,

I have a situation:

Its giving me the required schematic. (thats just fine and i am on
what
i want)

But the pins of a bus named as xyz[0] in verilog
are getting converted as xyz<0> in schematic.

Meaning [ ] the paranthesis as < > in sch.

Where should I set option to get the pins same name as verilog file?
Can you help ?