Building LVS netlist in the Cadence design flow

Hi all,

I have a question about the Cadence way of doing things.
We do not normally use Cadence software. But we
(an experienced VLSI design house) are
delivering a cell library to a customer which does
use Cadence software.

My problem is this: if you build a chip using SE
(SiliconEnsemble), what is the Cadence way of building
your LVS netlist, and how do you do this when you may have
multiple power domains (for instance, one vdd for pad drivers
and one vdd for the rest of the chip)?
In some designs, these two domains will be separate.
In other designs, they will be connected together on-chip.
The cell library needs to handle both situations.

(There is no corresponding problem with ground because
all ground nodes connect through the p-substrate).

I am guessing the flow is something like this:

1. Each cell has a spice netlist. Core cells have power
and ground as global nodes. Pads have ground as a global
node but their vdd nodes NOT global.

2. Specify chip connectivity using a verilog file.
This verilog file includes references to the two distinct
vdd ports on each pad, and specifies their connectivity also.

3. Run the verilog + spice netlists though some tool to
build a full chip layout-independent LVS netlist.

4. The LEF for pads does NOT include ports for the pad power
and ground rings. The pad rings are connected magically by
butting pads together (using filler cells if necessary).
(Because we do not want SE to attempt the actual routing
between pads).

5. Read the verilog file into SE when creating the floorplan.
There will be a discrepancy between the verilog and LEF
descriptions of pads (because verilog contains references
to the two vdd's, but LEF does not), but SE can cope with this.
(** This is the part that bothers me. I am
sure SE will NOT cope with the LEF and verilog not having
the same ports on pads).

6. SE places the chip according to this verilog netlist;
then you export GDSII and run (and hopefully pass) LVS.

Is that how it works? Or is the flow different?

Thanks in advance.

 

Right, that's not really a Cadence-specific question. Cadence
Assura reads top-level verilog with cell-level spice/CDL pretty
much transparently. If you're running Hercules you use nettran,
if you're using Calibre, Mentor gives you a little verilog->spice
converter.

Sounds fine. If you really wanted to, you could make the pad vdd
nets global also, and then short them or not at LVS run time
with LVS-tool-specific net-shorting hacks. But don't do that,
the explicit multi-supply connections on instances that you are
proposing is the right way to do it.

-Jay-

 

j

You have two choices:
- If you have schematic and complete Verilog gate netlist, Verilog-in
the verilog file using Cadence's NC Verilog.
- If you have CDS netlist, include the netlist as part of LVS run.