Buggy behaviour with Analog DE / Spectre and newline in input.scs

Hi,

I have a very annoying situation when simulating a design using the
analog design environment and spectre. I have included a diffAmp from
the ahdlLib and so the final line of my input.scs file reads:

ahdl_include "long path to verilog \
file"

Now I get the error message: bad include filename syntax: ("long path
to verilog).
Please notice that the last line somehow
gets swallowed by spectre. When I manually delete the backslash
and force everything onto one line I can simulate just fine. There
are many occurences of the backslash character in my input.scs file
and
spectre always continues to the new line, expept for this *darn" case.
Could anybody help me please, before I loose my mind ;-).

Regards
Mathias

 

Hi Mathias ,

For a quick solution/workaround you have two ways of influencing this:
- use the asimenv.* variable that defines the executable name, and point
it to a script. In the script you can use awk/sed/perl to collate the
wrapped line, and then call spectre with all arguments.
- use the flowchart mecanism of ADE to call this preprocessing.

 

The most likely is that you have hnlMaxLineLength set in a .simrc or .cdsinit
file somewhere.

hnlSoftLineLength is a better way of restricting the length, but best still is
to not set either...

You should not have to do the hacks that Frederic was suggesting.

Andrew.