batch of questions related to VXL :)

Hello All,


I have some question related to VXL. I'm using Cadence Ic5.1.41.

1)

I’m writing a skill script that establish connectivity (using VXL ) in
a layout.

I have a schematic, and all the subcells, in the library LIB_SCH.
This lib is read-only, and all the symbols / schematic inside refer to
this library.

I have a top layout, in the library LIB_LAY.
This lib contains all the layout cells used in the top layout.
The layout refer to the schematic in LIB_SCH.

Both LIB_SCH and LIB_LAY are “stand alone” libraries, except that
LIB_LAY refers to LIB_SCH for connectivity.

When I run VXL, after updating components and nets, it flags all my
layout instances, because the layout library is different from the
schematic library.

One workaround could be to use the lxUseCell property in the
schematic, but this one is read-only.

So I wanted to know if there is a variable I can set somewhere to say
VXL to use the all the layout cells in library LIB_LAY , and not to
care about the libname defined by the schematic ? (cellnames are
same )
(a kind of lxUseCell on the fly for a read only schematic...)



2)
My layout has some pins that use square brackets [], and same pins are
defined with angular brackets <> in my schematic.
How can i say to VXL to match [] pins with <> pins if basename is
same?

3)
Is it possible to say to VXL not to be case sensitive when it does the
extraction ?
It flags pins vdd (layout) and VDD (schematic)


May someone help me please ?

Thanks and regards,

bubu