Available: Open Source VHDL parser - for free

Discussion in 'Cadence' started by Sumit Gupta, Jul 13, 2004.

  1. Sumit Gupta

    Sumit Gupta Guest

    Hi all

    I wrote a VHDL parser as part of another larger software tool about 6
    years ago. The webpage, on which the parser is, is going to be
    retired soon. So, if anyone is interested, here is a link to my
    parser:

    http://www.cecs.uci.edu/~iesag/oldPage/Topts/

    Regards
    Sumit
     
    Sumit Gupta, Jul 13, 2004
    #1
  2. Sumit Gupta

    Kelvin Guest

    Got any Verilog parser?

    Kelvin
     
    Kelvin, Jul 13, 2004
    #2
  3. Sumit Gupta

    Phil Tomson Guest

    Phil Tomson, Jul 13, 2004
    #3
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