Automating the Simulation Process.

Dear all,

I have a model. The Model is shown in the following link below.

http://www.aisl.cyd.liu.se/temp/image.jpg

It has an
1) 8-bit Adder
2) a Verilog-A Module
3) Some VPWLF Sources which take "files" as inputs.

Some facts:
1) I have to simulate it for 8, 12 and 16 bit adders.
2) So the number of VPWLF sources also change accordingly and so does
the Verilog-A modules.

Now what I need to do is automate the whole process of simulating this
Model (with varied bit adders) using spectre. To be frank I am not sure
whether its worth it. Do i really need to automate this model and
simulate it ? or I can just go about doing this manually. Which one is
simpler ?

I have some Idea that the Automation has to be done using Ocean
Scripting language and SKILL. But not sure exactly how I can go about
doing this.

Thanks in advance,
kvaddina.

 

Hi,
thanks for your nice post. link to a picture, clear explanation, proper
english, this definitely deserves an answer.
I'll do my best...

I don't think so. If it's for 3 cases (8, 12 and 16 bits) then it would
probably be a lost of time trying to automate this in the general case.

It's not clear what you want to automate. OCEAN is great for running
simulations and extracting results, and since it's part of a
full-featured scripting (SKILL) language you can go about doing many
things - definitely worth putting your hands on it.

But when it comes to changing the circuit /topology/ (i.e. having
variable number of sources) then it can't do much for you. Still it's
feasible to modify you schematic accordingly before netlisting it, but
in my opinion for such kind of work it is easier to produce the netlist
yourself (or, at least, the varying part of it).

(I'm not sure i fully understood what you want to do, please give some
more if I didn't)

cheers,

stéphane

 

Hi Kvaddina and Stephane,

True. The automation will pay off only if you have to do those 3
simulations over and over ( for instance if you want to run over all
corners, temperatures, supply conditions, extracted views etc...)

It seems you do not need to change the topology, but only the content
of the PWL files and the verilogA model. So you can work at the file
level. Simply overwrite your files between each run and you are done.
for instance do:
/* __ */
foreach(wl list(8 12 16)
cmd=strcat(
"cp"
" "
"path/to/veriloga/model/mymodel_" sprintf(nil "%L" wl) ".va"
" "
"path/to/veriloga/model/mymodel.va"
)
system(cmd)

;;; do the same with the pwl files
;;; run your simulations and posprocess steps relevant for this "wl"
);foreach
/* __ */

Assuming you have named the files mymodel_8.va mymodel_12.va mymodel_16.va

 

ThankYou very much for your Replies Stephane and Fogh.

Well, I forgot to add a point. Not only that I need to Simulate the
whole Model with an Adder (8,12 and 16 bits) but also I have to
simulate it for Multiplier and Divider (both 8, 12 and 16 bits) as
well. So now the number of cases for me would be 9 or probably more if
I intend to do the combinations of Adders, Multipliers and Dividers.

Some Facts:

1) Extracting data/Interpreting data will be done by my Verilog-A
Module.

2) I am NOT going to Simulate my Model for all corners, temperatures,
supply conditions or extracted views etc...

3) I will be changing my Circuit topology. That is, the number of PWL
Files/Sources changes with every simulation but they are CONSTANT for a
particular simulation. so does the Verilog-A module and the Design
(Adder, Multiplier, Divider or a combination of them).

What I want to Do:

1) Simulate my Model shown in the picture and as explained above (The
number of such models that I need to simulate will be 9 or more). So
the Number of VPWLF sources changes with every simulation so does the
Verilog-A module. So I strongly believe that I need to automate this
process of Simulation. Since doing this manually would be a tedious
task. I am looking for suggestions from you in what way I can go about
doing this automation.

"Working at File level" as suggested by Fogh seems interesting. Will
this be feasible with the new facts that have I put in this post ?

Thanks and Regards,
Kvaddina.

 

Any one out there who could comment on my post ?? Thanks in advance.

Kvaddina.

 

There are many many ways to do this. On could imagine, for example, have a function generate a file
containing the stimuli and verilog-a for a specified number of bits.

i will assume, for simplicity, there is always two input ports named A and B, and
one output port named Y. this is easily adapted.

note, this code is only for demonstrating. i didn't use it or test it.

hope this will help
good luck

stéphane

NB: instead of this, one could imagine generating a new schematic on-the-fly, for example.
or, have a perl script generate the whole netlist, then run spectre from command-line.
or, ...


;;
;; this procedure generates a file with instance statements for sources driving the bus
;; netName<1:netSize>. sources are vpwlf with the file being netName_bitX.pwl
;;

procedure( _KVGenStimuli( netName netSize fileName )
let( (fh)
fh = outfile( fileName )
for( i 1 netSize
fprintf( fh "V%s%d (%s<%d> 0) vsource type=pwl file=%s_bit%d.pwl\n" netName i netName i netName i )
) ; for
close(fh)
) ; let
) ; procedure

;;
;; this one generate a file with an instance statement for a block with given name,
;; and connects it to the given bus netName<1:netSize>
;;

procedure( _KVGenMeasure( model netName netSize fileName )
let( (fh)
fh = outfile( fileName )
fprintf( fh "meas block_%d_bits ( " netSize )
for( i 1 netSize
fprintf( fh "%s<%d> " netName i )
) ; for
fprintf( fh ")\n" )
close(fh)
) ; let
) ; procedure

;;
;; this procedure simulates the given lib/cell/view
;;

procedure( KVSimulate( lib cell view )

let( ( cv portA portB portY sizeA sizeB sizeY )
; open the cellview
unless( cv = dbOpenCellViewByType( lib cell view nil "r" nil )
error("Cannot open cellview")
) ; unless

; locate the A port
unless( portA=car(exists( x cv~>terminals rexMatchp( "A<[0-9]+:[0-9]+>" x~>name ) ))
error("Port A not found")
) ; unless
sizeA = portA~>numBits

; locate the B port
unless( portB=car(exists( x cv~>terminals rexMatchp( "B<[0-9]+:[0-9]+>" x~>name ) ))
error("Port B not found")
) ; unless
sizeB = portB~>numBits

; locate the Y port
unless( portY=car(exists( x cv~>terminals rexMatchp( "Y<[0-9]+:[0-9]+>" x~>name ) ))
error("Port Y not found")
) ; unless
sizeY = portY~>numBits

dbClose(cv)

; generate stimuli for port A (sizeA bits)
_KVGenStimuli( "A" sizeA "/tmp/KVstimuli_A.scs" )

; generate stimuli for port B (sizeB bits)
_KVGenStimuli( "B" sizeB "/tmp/KVstimuli_B.scs" )

; generate verilog-A block for port Y (sizeY bits)
_KVGenMeasure( "mymodel" "Y" sizeY "/tmp/KVmeasure_Y.scs" )

;; netlist and run
simulator('spectre)

;; open design
when( !design( lib cell view )
error("Couldn't open design for simulation")
) ; when

;; add stimulus files
;; the measurement file is not exactly a stimulus, well... should work
stimulusFile( "/tmp/KVstimuli_A.scs" "/tmp/KVstimuli_B.scs" "/tmp/KVmeasure_Y.scs" ?xlate t )

;; configure model files, includes etc...
;;

;; configure simulation
analysis( 'tran ?stop 10u )

;; run
run()

;; etc... etc...

;; delete the temporary files
deleteFile("/tmp/KVstimuli_A.scs")
deleteFile("/tmp/KVstimuli_B.scs")
deleteFile("/tmp/KVmeasure_Y.scs")
) ; let
) ; procedure

 

Thanks a lot Stephane. I am working on your inputs.

Regards,
Kvaddina.