I try to extract an existing layout without a LVS check. Therefore, i created an adequate rsf and ran assura. The problem is now, that the created netlist include all transistors and parasitic devices, but all transistors are generated as an hierachical instance like this: mavi40400\/avd511_2 ( gnd\!\#185 vdd\!\#317 gnd\!\#185 gnd\!\#185 ) n l=0u w=0u mavi40400\/avd511_3 ( gnd\!\#185 vdd\!\#317 gnd\!\#185 gnd\!\#185 ) n l=0u w=0u How to solve this problem? LG Michael
