ASSURA netlist question

Hi,

I'm using assura 2 & 3 depending on project. We have always generated
CDL netlists and used a toplevel.v for our chip LVS.

Is it possible to mix netlist formats?

We would like to use a mixture of dfII schematics, CDL's and .v files.
(I'm having trouble trying to set this up and wonder where I'm going wrong).

thanks in advance,
Chris

 

Hi Chris,

We use succesful various combinations of netlists:

1)
Verilog + CDL (generated with export->CDL / auCdl netlister)

2)
Verilog + dfII schematics (using the dfIIToVldb translator).
Depending on your library you should use auLvs/auCdl or another view.


My view: Assura supports any mix of formats (having some minor bugs
in the past), but the library you're using should support the netlister
you like to use.

regards, Jacob

 

You're not going wrong, you cannot do it.

At least in 2.0, mixing all three is not supported and non-functional,
period. In general, mixing Verilog and dfII in Assura is harder than
you would think because Verilog is handled by using van to convert
it to dfII, *then* dfIIToVldb-ing it in.

If you really had to, you could run van yourself (or probably
File->import Verilog from Virtuoso) and just explicitly treat it
as another dfII library. But then you have to keep that up to
date, a bit of a pain.

Mixing all three is advertised to work in 3.0, but does not
(at least as of 3.0.5). PCR 557163. It may work in 3.1, I
haven't tried yet.

What most people do is set up CDL netlisting out of dfII and
go all-netlist, Verilog calling CDL. This works great.

Jay <jayl at accelerant dot net>