Assura LVS problem and top level pins

Hi folks,
I want to share a problem I am trying to solve for a long time.

During Assura LVS, the netlist generator takes care of the top level
pins, that is very well known. However, as far as I understood from
thousand of trials, Assura LVS does not care about the layout pins of
the lower level circuits. Let me tell this as an example. I have a
big decoder (cell name DEC), lets say. Assura LVS matches the decoder
schematic and layout, there is no problem. however, when I use this
decoder in a larger cell, the LVS does not match and gives some
problems with the decoder which has passed from LVS recently. The
reason is this: Since DEC is not the top level circuit, the LVS
algorithm does not care about its layout pins and solves the circuit
arbitrariry. There are tens of solutions for a decoder, as known.
And, when the algorithm makes sure that all the lower level cells are
passed from LVS and goes into the top level LVS match, the top level
circuit does not pass since the arbitrarily mathced DEC is not the
real solution.

So what I want from LVS is to take care of the lower level cells
layout pins, that is all.

The documented solution to this is to use pin swappability. However,
I could not enable pin swapping succesfully yet. At least, the pin
swapping does not work as I want.

Do you have any comment on this problem?

Regards

 

a top level misconnect can be be falsely reported at a lower level.
Does DEC get expanded?
If so, try setting the parent options. Also, make sure that the
check schematic/layout pins are
enabled. Another thing you could try is to blackbox DEC or
instantiate a schematic and layout
with only pins and see if a top level error is flagged. Post back
the outcome and we can go from
there

Good Luck!!!

Rick