Assura connection via substrate

Discussion in 'Cadence' started by Ozgur.Ates, Sep 15, 2008.

  1. Ozgur.Ates

    Ozgur.Ates Guest

    Hi,

    I am using AMS C35B4 process and I want to seperate AGND and DGND in
    my layout design, however ASSURA LVS gives error because of soft
    connection of these two grounds through substrate. Thanks in advance
    for any help.

    Ozgur
     
    Ozgur.Ates, Sep 15, 2008
    #1
  2. Ozgur.Ates

    Riad KACED Guest

    Hi Ozgur,

    When you say 'I want to separate AND and DGND in my layout design', do
    you mean a physical separation or a logical separation ?

    1. In case of the latter, many PDKs do support CAD markers/layers that
    allows you to logically isolate a part of a substrate from the global
    substrate. You may need to check your PDK for this feature. Bear in
    mind that this isolation is not physical but rather a way to tell your
    LVS engine you've got two separate substrates so it would allow you
    connecting them to different nets.

    2. In case of the former, some foundries/processes do support a triple
    wells with the use of deep-nwell. The deep-nwell combined with the
    nwell lets you building an isolated Pwell in your global substrate.
    This is the solution to physically isolate your analog blocs from
    digital ones, it is good for noise isolation. This solution is not for
    free though, it does involve one additional mask at least.

    These are the 2 ways I have been working with so far.

    If you have not got any of those solutions, then you might be
    interested in the Assura multiple ground solution. It is described in
    Chapter 9 of the Assura Physical Verification User Guide -> Chapter 9 -
    do admit I'm more familiar with Calibre in this area and my best
    advice is just to follow the instructions as shown in the doc.

    Hope this helps.
    Riad.
     
    Riad KACED, Sep 15, 2008
    #2
  3. Ozgur.Ates

    Ozgur.Ates Guest

    Hi Riad,

    Thank you for your answers. I meant to seperate two grounds logically.
    After your I advise, I check AMS 0.35um design kit but I could not
    find an available CAD layer to seperate different substrate areas
    logically for Assura DRC/LVS

    Regards,
    Ozgur
     
    Ozgur.Ates, Sep 17, 2008
    #3
  4. Ozgur.Ates

    Riad KACED Guest

    Hi Ozgur,

    You are in trouble without those markers I'm afraid :-(
    You can go for the last option, i.e make use of the Assura options.
    You can try the joinNets as explained in the assura user but it is a
    bit tricky for ground connections I'm afraid. It's pretty much easy to
    make virtual connection on signal nets/pins but it is less for ground
    nets/pins. Why ?
    1. Because almost all the PDK check for multiple stamping of the
    substrate using the geomStamp command
    2. The substrate pin extraction on devices could be messed up if you
    disable the multiple stamping check.
    My experience using Assura for this specific need is not good enough
    to give you any solid advice.
    I have always been working in either options 1 or 2 as explained
    above.
    Personally, I won't go for any virtual connections for multiple
    grounds, this could be very harmful ...

    Hope you will get more helpful comments on this :)

    Cheers,
    Riad.
     
    Riad KACED, Sep 18, 2008
    #4
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