AMS simulation

Discussion in 'Cadence' started by Guneet Singh, May 25, 2004.

  1. Guneet Singh

    Guneet Singh Guest

    Hello everyone,
    I am facing a problem with the Verilog-AMS model simulation. I am
    using the Cadence LDV-4.1 toolset and trying to simulate a simple
    resistor model with an analog control file (the test bench).
    The first two steps (compilation and elaboration) are working fine
    and I am not getting any errors. However when I simulate using ncsim,
    I get an error. I am using using the resistor model that is in the
    ncvlog manual just for checking whether the tool is working or not. I
    am listing all the messages that I get when I execute the commands.
    The hdl.var and cds.lib files are also included.

    NCVLOG:

    ~/verilog11-9> ncvlog -ams -messages trial.vams
    ncvlog: 04.10-s022: (c) Copyright 1995-2003 Cadence Design
    Systems, Inc.
    file: trial.vams
    module worklib.restor:module
    errors: 0, warnings: 0



    NCELAB:

    ~/verilog11-9> ncelab -messages worklib.restor:module
    ncelab: 04.10-s022: (c) Copyright 1995-2003 Cadence Design
    Systems, Inc.
    Elaborating the design hierarchy:
    Discipline resolution Pass...
    Building instance overlay tables: ....................
    Done
    Loading native compiled code: ....................
    Done
    Building instance specific data structures.
    Design hierarchy summary:
    Instances Unique
    Modules: 1 1
    Interconnect: 2 -
    Writing initial simulation snapshot:
    worklib.restor:module
    Elaborating analog portion of the design hierarchy:
    libsyracuse: @(#)$CDS: libsyracuse version
    12/17/2003 03:11 (ncss21) $(sub-version 1217 )



    NCSIM:

    ~/verilog11-9> ncsim -amslic -messages -analogcontrol trial.scs
    worklib.restor:module
    ncsim: 04.10-s022: (c) Copyright 1995-2003 Cadence Design
    Systems, Inc.
    Loading snapshot worklib.restor:module .................... Done
    Starting analog simulation engine...
    libpalermo: @(#)$CDS: libpalermo version
    12/17/2003 03:11 (ncss21) $(sub-version 1217 )

    Analog Kernel using -ANALOGCONTROL trial.scs.

    Error found by spectre during circuit read-in.
    trial.scs: RESTOR is an instance of an undefined model
    restor.

    spectre terminated prematurely due to fatal error.
    ncsim: *E,RNAERR: Simulation is complete, analog initialization
    error.


    CDS.LIB:

    INCLUDE /opt/CAD/Cadence/LDV-4.1/tools/inca/files/cds.lib
    DEFINE worklib ./worklib


    HDL.VAR:

    SOFTINCLUDE $LDV-4.1/tools/inca/files/hdl.var
    define ncuse5x
    define cdslib ./cds.lib
    DEFINE LIB_MAP (./ => worklib)
    DEFINE worklib ./worklib


    # Define view mapping.
    # Files with .vb extension are compiled into view beh
    # Files with .vr extension are compiled into view rtl
    # Files with .vg extension are compiled into view gates
    # Files with .vams extension are compiled into view module
    DEFINE VIEW_MAP (.vb => beh, \
    ..vr => rtl, \
    ..vg => gates, \
    ..vams => module)


    I am clueless as to why the simulator is not able to locate the
    restor model. I would greatly appreciate if someone could suggest me a
    solution to this problem.

    Thanks and regards,
    Guneet
     
    Guneet Singh, May 25, 2004
    #1
  2. Please show us trial.vams and trial.scs; that will help us to explain the
    problem. Trying to debug from the error messages alone is rather hard!

    Thanks,

    Andrew.
     
    Andrew Beckett, May 25, 2004
    #2
  3. Guneet Singh

    Guneet Singh Guest

    Mr Beckett,
    I'm sorry, I forgot to include the model file and the control file
    along with the listing.
    Here they are:

    trial.vams :

    `include "disciplines.vams"
    `include "constants.h"

    module restor(p,n);
    inout p,n;
    electrical p,n;
    parameter real r=0;

    analog
    V(p,n) <+ r*I(p,n);

    endmodule


    trial.scs:

    simulator lang=spectre
    global gnd

    ahdl_include "trial.vams"

    ir in gnd isource dc=1m
    r1 in gnd restor r=1K

    saveNodes options save=allpub
    paramSwp dc start=1 stop=1001 param=r dev=r1


    I would be grateful if you could help me out on this.

    Thanks,
    Guneet
     
    Guneet Singh, May 26, 2004
    #3
  4. Hi Guneet,

    What you're doing doesn't make sense. Your control file for AMS is actually a
    spectre netlist, whereas it should only contain the options and analyses (just
    tran in practice).

    You can do the simulation just by running spectre:

    spectre trial.scs

    with what you have. If you want to use AMS Designer, you'd need to have the
    top level as a Verilog-AMS netlist. For example:

    `include "disciplines.vams"
    module top;
    electrical in,gnd;
    isource #(.dc(1m)) ir (in, gnd);
    restor #(.r(1K)) r1 (in, gnd);
    endmodule

    Then compile this:

    ncvlog -ams top.vams

    as well as the trial.vams you already compiled.

    Then have a control file such as this:

    //
    tran tran stop=100n

    And run:

    ncsim -ams -analogcontrol control.scs worklib.top:module

    You can then use the UI:

    ncsim -ams +gui -analogcontrol control.scs worklib.top:module

    etc as well.

    In this case there's no digital, and so you might as well just use spectre, but
    I'm assuming you're going to develop it into something bigger.

    Regards,

    Andrew.
     
    Andrew Beckett, May 26, 2004
    #4
  5. Guneet Singh

    Guneet Singh Guest

    Mr. Beckett,
    Thanks a lot for the help. The simulation worked this time. I am
    indeed very grateful to you.
    Thanks and regards,
    Guneet
     
    Guneet Singh, May 26, 2004
    #5
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