ams simulation of std cells

Discussion in 'Cadence' started by DReynolds, May 22, 2007.

  1. DReynolds

    DReynolds Guest

    I am trying to run a mixed signal simulation and if I use the
    functional views of the std cells provided by the vendor, I get errors
    in the config window saying that and, not, buf have no views
    associated with them. I thought these were verilog primitives, does
    anyone know what I have to do to get ams to accept these?


    thanx

    David
     
    DReynolds, May 22, 2007
    #1
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads

  1. AMS simulation

  2. how to run VHDL-AMS Simulation in Cadence

  3. VHDL-Ams AMS Designer

  4. Problems with ncsim and ams simulation

  5. Filtering DRC errors from std. cells with assura

  6. Problems in opening OSU std cells for PDK45nm in virtuoso

  7. custom digital placer placing blocks of 2 standard cell height alongwith normal std cells

  8. V8 Cells vs. V7 Cells

Loading...