Ambit/PKS - Timing problem

Hiya!
The static timing analysis of Ambit (as well as the one of Pearl)
puzzles me. I only have positive triggered flip-flops in my design. So
why is the first FF state_reg_1 in the delay list triggered by the
negative clock?

This is the timing report:

Path 1: MET Setup Check with Pin CP/fault_detect_reg/C
Endpoint: CP/fault_detect_reg/D (^) checked with leading edge of
'MASTER'
Beginpoint: WC/state_reg_1/Q (v) triggered by trailing edge of
'MASTER'
Other End Arrival Time 0.00
- Setup 0.85
+ Phase Shift 40.00
= Required Time 39.15
- Arrival Time 38.67
= Slack Time 0.48
+---------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay |
Arrival | Required |
| | | | |
Time | Time |
|---------------------+--------------+---------------+-------+---------+----------|
| | clk v | | |
20.00 | 20.48 |
| WC | clk v | WBIST_CONTROL | |
20.00 | 20.48 |
| WC/state_reg_1 | C v -> Q v | DFRRX1 | 0.05 |
20.05 | 20.53 |
| WC/i_3 | B v -> Q v | AND2X1 | 2.55 |
22.60 | 23.08 |
| WC/i_10 | A v -> Q v | AND2X1 | 2.46 |
25.07 | 25.55 |
| WC/i_19476 | A v -> Q v | AND2X1 | 2.30 |
27.37 | 27.85 |
| WC/i_1315 | A v -> Q v | OR3X1 | 1.87 |
29.24 | 29.72 |
| WC/i_435 | A v -> Q v | BUX4 | 2.06 |
31.30 | 31.78 |
| WC/i_1246 | IN0 v -> Q v | MU2X1 | 1.77 |
33.08 | 33.56 |
| WC/i_434 | A v -> Q v | BUX4 | 1.98 |
35.05 | 35.53 |
| WC | tdi[0] v | WBIST_CONTROL | |
35.05 | 35.53 |
| CP | tdi[0] v | COMPARATOR | |
35.05 | 35.53 |
| CP/i_34 | S v -> Q v | MU2X1 | 1.95 |
37.00 | 37.48 |
| CP/i_0101 | A v -> Q ^ | NA2X1 | 0.52 |
37.53 | 38.00 |
| CP/i_1548 | B ^ -> Q ^ | AND3X1 | 1.15 |
38.67 | 39.15 |
| CP/fault_detect_reg | D ^ | DFRRX1 | 0.00 |
38.67 | 39.15 |
+---------------------------------------------------------------------------------+