Ambit issue

Hi freinds

I am using Ambit to synthesize my rtl. I first read lca300k.alf
followed by my rtl. Though the rtl does not have any bug, the ambit is
complaining about something like

==> ERROR: No clock is defined in the always block (File iceport_tap.v,
Line 67) <VLOGPT - 412>

I dont have any idea why I am getting this error since when I use DC,
the rtl is synthesized without any error. For ref purpose, the rtl is
given below.




module tap(
Trst_n,
Tclk,
tms,
capture_ir,
capture_dr,
update_ir,
update_dr,
shift_ir,
shift_dr,
idle_st,
tlr,
shift_dr_next,
exit2_dr
);

input Trst_n;
input Tclk;
input tms;

output capture_ir;
output capture_dr;
output update_ir;
output update_dr;
output shift_ir;
output shift_dr;
output idle_st;
output tlr;
output shift_dr_next;
output exit2_dr;

reg [3:0] next_st;
reg [3:0] pres_st;



// Latch next state values
always@ (negedge Trst_n, posedge Tclk )
begin
if (!Trst_n)
pres_st <= `JTAG_STATE_TLR;
else if (Tclk)
pres_st <= next_st;
end

// Export state

assign capture_ir= (pres_st == `JTAG_STATE_CAPT_IR) ? 1'b1 : 1'b0;
assign capture_dr= (pres_st == `JTAG_STATE_CAPT_DR) ? 1'b1 : 1'b0;
assign update_ir = (pres_st == `JTAG_STATE_UPDT_IR) ? 1'b1 : 1'b0;
assign update_dr = (pres_st == `JTAG_STATE_UPDT_DR) ? 1'b1 : 1'b0;
assign shift_ir = (pres_st == `JTAG_STATE_SCAN_IR) ? 1'b1 : 1'b0;
assign shift_dr = (pres_st == `JTAG_STATE_SCAN_DR) ? 1'b1 : 1'b0;
assign idle_st = (pres_st == `JTAG_STATE_IDLE) ? 1'b1 : 1'b0;
assign tlr = (pres_st == `JTAG_STATE_TLR) ? 1'b1 : 1'b0;
assign shift_dr_next = (next_st == `JTAG_STATE_SCAN_DR) ? 1'b1 : 1'b0;
assign exit2_dr = (pres_st == `JTAG_STATE_EXIT2_DR) ? 1'b1 :1'b0;


//********************************************************
// Next state logic
//********************************************************

always@ (pres_st, tms)
begin
case (pres_st)

`JTAG_STATE_TLR : begin
if (!tms)
next_st= `JTAG_STATE_IDLE;
else if(tms)
next_st = `JTAG_STATE_TLR;
end

`JTAG_STATE_IDLE : begin
if (!tms)
next_st = `JTAG_STATE_IDLE;
else if(tms)
next_st = `JTAG_STATE_SEL_DR;
end

`JTAG_STATE_SEL_DR : begin
if (!tms)
next_st = `JTAG_STATE_CAPT_DR;
else if (tms)
next_st = `JTAG_STATE_SEL_IR;
end


`JTAG_STATE_SEL_IR : begin
if (!tms)
next_st = `JTAG_STATE_CAPT_IR;
else if (tms)
next_st = `JTAG_STATE_TLR;
end


`JTAG_STATE_CAPT_DR : begin
if (!tms)
next_st = `JTAG_STATE_SCAN_DR;
else if (tms == 1)
next_st = `JTAG_STATE_EXIT1_DR;
end


`JTAG_STATE_SCAN_DR : begin
if (!tms)
next_st = `JTAG_STATE_SCAN_DR;
else if (tms)
next_st = `JTAG_STATE_EXIT1_DR;
end


`JTAG_STATE_EXIT1_DR : begin
if (!tms)
next_st = `JTAG_STATE_DPAUSE;
else if (tms)
next_st = `JTAG_STATE_UPDT_DR;
end


`JTAG_STATE_DPAUSE : begin
if (!tms)
next_st = `JTAG_STATE_DPAUSE;
else if (tms)
next_st = `JTAG_STATE_EXIT2_DR;
end


`JTAG_STATE_EXIT2_DR : begin
if (!tms)
next_st = `JTAG_STATE_SCAN_DR;
else if (tms)
next_st = `JTAG_STATE_UPDT_DR;
end


`JTAG_STATE_UPDT_DR : begin
if (!tms)
next_st = `JTAG_STATE_IDLE;
else if (tms)
next_st = `JTAG_STATE_SEL_DR;
end


`JTAG_STATE_CAPT_IR : begin
if (!tms)
next_st = `JTAG_STATE_SCAN_IR;
else if (tms)
next_st = `JTAG_STATE_EXIT1_IR;
end


`JTAG_STATE_SCAN_IR : begin
if (!tms)
next_st = `JTAG_STATE_SCAN_IR;
else if (tms)
next_st = `JTAG_STATE_EXIT1_IR;
end


`JTAG_STATE_EXIT1_IR : begin
if (!tms)
next_st = `JTAG_STATE_IPAUSE;
else if (tms)
next_st = `JTAG_STATE_UPDT_IR;
end



`JTAG_STATE_IPAUSE : begin
if (!tms)
next_st = `JTAG_STATE_IPAUSE;
else if (tms == 1)
next_st = `JTAG_STATE_EXIT2_IR;
end


`JTAG_STATE_EXIT2_IR : begin
if (!tms)
next_st = `JTAG_STATE_SCAN_IR;
else if (tms)
next_st = `JTAG_STATE_UPDT_IR;
end


`JTAG_STATE_UPDT_IR : begin
if (!tms)
next_st = `JTAG_STATE_IDLE;
else if (tms == 1)
next_st = `JTAG_STATE_SEL_DR;
end


default: next_st = `JTAG_STATE_IDLE; // For all the 9 state
logic states

endcase
end
endmodule

//************************************ End of File
**************************************//



Kindly help me out guys.
Thanks
Rik

 

^^^^^
This your problem. Basically you don't need "if (Tclk)" as the
"posedge Tclk" is assumed if it wasn't the reset which caused the
begin/end to execute.

 

That doesn't make any sense. If thats the case, why should DC
synthesize.
Thats not the problem. There is something else to it.


Ritwik

 

Well, did you try it ?
DC is a much older tool with a much larger user set which apparently
makes a much larger set of errors. Ambit being much newer doesn't have
this experience.

If you say so, but I think you should try the change and then compare
the generated logic to what DC (btw you verified that the gate level
from DC is what you want, right?) gave you.
The reason Ambit is complaining about your code IS because you have
the "if(clk)" in your non-reset path, that is for certain. If you want
more information on this, get the Verilog synthesizable subset
standard (yes, there is one) and read how registers with async reset
are inferred.