Hello, I would like to create a database that includes the time events classified by type of primitive gate and that could be used with circuits around 32Kgates (no so big). It seems easy to create a sst2 database of such characteristics using the signalscan directive $recordvars in verilog but I dont know how I can get access to this information from some external program , I need this information to perform and analysis before the simulation. is it posible?, any other suggested method?. Thanks in advance, -------------------------------------------------- Juan F. Osorio Universitat Politècnica de Catalunya High Performance Integrated Circuits Design Group http://pmos.upc.es/blues/ Bulding C4, Campus Nord C/ Jordi Girona, 1-3 ES-08034 Barcelona -Spain --------------------------------------------------
