Cadence

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  1. vidhya

    Stretch option in Virtuoso

    vidhya, Sep 3, 2003
    Replies:
    1
    Views:
    868
    suresh j
    Sep 3, 2003
  2. walala

    why SE KEEPS telling me that I don't have clock net?

    walala, Sep 2, 2003
    Replies:
    1
    Views:
    993
    Muzaffer Kal
    Sep 3, 2003
  3. walala

    why cannot I pass the "Cell Placement" in SE? The site utilization is = 140.2 is too high! Impossibl

    walala, Sep 2, 2003
    Replies:
    1
    Views:
    1,292
    Muzaffer Kal
    Sep 3, 2003
  4. Badhrinath Jagannathan

    cdsSpice debugging!

    Badhrinath Jagannathan, Aug 31, 2003
    Replies:
    1
    Views:
    833
    B
    Sep 2, 2003
  5. Andy

    What is the potential difference between HSPICE and Spectre ?

    Andy, Sep 2, 2003
    Replies:
    1
    Views:
    1,133
    Erik Wanta
    Sep 2, 2003
  6. Hristo Brachkov

    Problems with Cadence on Solaris 9

    Hristo Brachkov, Aug 20, 2003
    Replies:
    3
    Views:
    957
    Hristo Brachkov
    Sep 2, 2003
  7. S. Badel

    alternate waveform viewer

    S. Badel, Aug 28, 2003
    Replies:
    2
    Views:
    913
    Hristo Brachkov
    Sep 2, 2003
  8. Taivo Saarts

    Delete a cell in SKILL

    Taivo Saarts, Sep 1, 2003
    Replies:
    2
    Views:
    1,042
    S Hazen
    Sep 2, 2003
  9. selvakumar_in

    ERC_error

    selvakumar_in, Sep 1, 2003
    Replies:
    0
    Views:
    651
    [email protected]
    Sep 1, 2003
  10. Petrus

    SEPKS block placement

    Petrus, Sep 1, 2003
    Replies:
    0
    Views:
    971
    Petrus
    Sep 1, 2003
  11. Petrus

    Silicon Ensemble 5.4 TLF Problem

    Petrus, Sep 1, 2003
    Replies:
    0
    Views:
    839
    Petrus
    Sep 1, 2003
  12. boki

    How's the accuracy about simulation MOS working at subthreshold region?

    boki, Aug 29, 2003
    Replies:
    0
    Views:
    836
    boki
    Aug 29, 2003
  13. John Gianni

    Which virtuoso layers are reserved?

    John Gianni, Aug 28, 2003
    Replies:
    0
    Views:
    888
    John Gianni
    Aug 28, 2003
  14. Abha

    Hierarchical POWER_GROUP

    Abha, Aug 28, 2003
    Replies:
    0
    Views:
    766
    Abha
    Aug 28, 2003
  15. Jack_Rabbit

    APD/Allegro SKILL Question -- Newbie SKILL User

    Jack_Rabbit, Aug 27, 2003
    Replies:
    0
    Views:
    1,569
    Jack_Rabbit
    Aug 27, 2003
  16. Erik Wanta

    *Error*outputs: digital terminal outputs not supported

    Erik Wanta, Aug 26, 2003
    Replies:
    0
    Views:
    885
    Erik Wanta
    Aug 26, 2003
  17. Ma Pu

    Display Problem

    Ma Pu, Aug 24, 2003
    Replies:
    0
    Views:
    967
    Ma Pu
    Aug 24, 2003
  18. S.T.

    Problems with ORCAD Layout

    S.T., Aug 22, 2003
    Replies:
    0
    Views:
    964
    S.T.
    Aug 22, 2003
  19. Erik Wanta

    move figures AND wires in schematic with SKILL

    Erik Wanta, Aug 22, 2003
    Replies:
    1
    Views:
    1,669
    Andrew Beckett
    Aug 22, 2003
  20. Perrin Bauer

    HSpice 2002, Affirma, MIxed-Mode

    Perrin Bauer, Aug 21, 2003
    Replies:
    1
    Views:
    812
    Erik Wanta
    Aug 21, 2003
  21. girish

    ocean script read-in error

    girish, Aug 21, 2003
    Replies:
    0
    Views:
    999
    girish
    Aug 21, 2003
  22. JC7

    Help - Diva DRC / ChagedLayer

    JC7, Aug 13, 2003
    Replies:
    1
    Views:
    1,001
    Andrew Beckett
    Aug 19, 2003
  23. Min Pan

    Running simulation using assura extracted view

    Min Pan, Aug 19, 2003
    Replies:
    1
    Views:
    889
    Erik Wanta
    Aug 19, 2003
  24. Erik Wanta

    _dbfCreateStrongGroup

    Erik Wanta, Aug 14, 2003
    Replies:
    2
    Views:
    669
    Erik Wanta
    Aug 19, 2003
  25. John Gianni

    New DFII cdsLibDebug UNIX/Linux command

    John Gianni, Aug 18, 2003
    Replies:
    0
    Views:
    849
    John Gianni
    Aug 18, 2003
  26. John Gianni

    SKILL listFunctions is now 6x faster than before

    John Gianni, Aug 18, 2003
    Replies:
    0
    Views:
    710
    John Gianni
    Aug 18, 2003
  27. Min Pan

    LVS problem using Assura LVS

    Min Pan, Aug 16, 2003
    Replies:
    0
    Views:
    2,232
    Min Pan
    Aug 16, 2003
  28. Gera

    Interfacing ConceptHDL with another process using SKILL

    Gera, Aug 16, 2003
    Replies:
    0
    Views:
    843
    Gera
    Aug 16, 2003
  29. Hari

    question regarding tech files and standard cells

    Hari, Aug 15, 2003
    Replies:
    0
    Views:
    846
    Hari
    Aug 15, 2003
  30. Peter Ballard

    pipo strmout and skill path

    Peter Ballard, Aug 14, 2003
    Replies:
    1
    Views:
    1,562
    JC7
    Aug 14, 2003
  31. Mike Russell

    geomSize

    Mike Russell, Aug 1, 2003
    Replies:
    10
    Views:
    1,071
    Kholdoun TORKI
    Aug 14, 2003
  32. Ashish

    Problem with Layout ... Urgent

    Ashish, Aug 14, 2003
    Replies:
    0
    Views:
    700
    Ashish
    Aug 14, 2003
  33. eda support guy

    capture output sent to poport in a list

    eda support guy, Aug 13, 2003
    Replies:
    0
    Views:
    797
    eda support guy
    Aug 13, 2003
  34. Peter Ballard

    bogus? error message from pipo

    Peter Ballard, Aug 12, 2003
    Replies:
    2
    Views:
    978
    Peter Ballard
    Aug 13, 2003
  35. vidhya

    Help regarding Virtuoso Layout editor....

    vidhya, Aug 6, 2003
    Replies:
    4
    Views:
    1,107
    Andrew Beckett
    Aug 12, 2003
  36. Matt Ziegler

    Ocean Netlisting

    Matt Ziegler, Aug 11, 2003
    Replies:
    1
    Views:
    1,121
    Jay Lessert
    Aug 11, 2003
  37. Michael Durr

    Spectre simulation ADE vs command line

    Michael Durr, Aug 1, 2003
    Replies:
    4
    Views:
    1,515
    Michael Durr
    Aug 11, 2003
  38. jo

    verilog code to netlist

    jo, Aug 4, 2003
    Replies:
    1
    Views:
    941
    B
    Aug 11, 2003
  39. Ricky Hardy

    Allegro 14.2 Board Wizard Bug

    Ricky Hardy, Aug 9, 2003
    Replies:
    1
    Views:
    808
    daytripper
    Aug 9, 2003
  40. Erik Wanta

    redisplay form on invalid input?

    Erik Wanta, Jul 26, 2003
    Replies:
    12
    Views:
    1,366
    Edward J Kalenda
    Aug 8, 2003
  41. Hari

    bind keys not enabled

    Hari, Aug 8, 2003
    Replies:
    1
    Views:
    999
    Andrew Beckett
    Aug 8, 2003
  42. Mike Russell

    Composer grid dots

    Mike Russell, Aug 7, 2003
    Replies:
    1
    Views:
    918
    Jay Lessert
    Aug 8, 2003
  43. Karthik Sundararaman

    siminfo error while creating netlist

    Karthik Sundararaman, Aug 4, 2003
    Replies:
    5
    Views:
    1,116
    Erik Wanta
    Aug 7, 2003
  44. Matthew E Rosenthal

    extract and LVS my own device

    Matthew E Rosenthal, Aug 6, 2003
    Replies:
    4
    Views:
    1,058
    S. Badel
    Aug 7, 2003
  45. S. Badel

    bandwidth()

    S. Badel, Aug 6, 2003
    Replies:
    1
    Views:
    756
    Erik Wanta
    Aug 7, 2003
  46. Dionis

    SJF, TJF licenses

    Dionis, Aug 3, 2003
    Replies:
    2
    Views:
    820
    Andrew Beckett
    Aug 6, 2003
  47. selvakumar_in

    modifying_drc

    selvakumar_in, Aug 5, 2003
    Replies:
    1
    Views:
    793
    S. Badel
    Aug 6, 2003
  48. Erik Wanta

    SKILL Progress Bar

    Erik Wanta, Aug 4, 2003
    Replies:
    2
    Views:
    993
    John Gianni
    Aug 6, 2003
  49. spias

    about first encounter

    spias, Aug 5, 2003
    Replies:
    0
    Views:
    959
    spias
    Aug 5, 2003
  50. cupric

    Simulating phase noise for PFD-CP

    cupric, Aug 4, 2003
    Replies:
    1
    Views:
    1,237
    Vikas Vijay
    Aug 5, 2003
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