Cadence

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  1. Echo

    SOS！What's wrong in the tf of Abstract generator would cause SEGV error??

    Echo, Feb 24, 2004
    Replies:
    0
    Views:
    1,010
    Echo
    Feb 24, 2004
  2. dati_remo

    Extraction Problem with divaEXT.rul

    dati_remo, Feb 24, 2004
    Replies:
    0
    Views:
    734
    [email protected]
    Feb 24, 2004
  3. roland

    How to setup ADE on CIW by using SKILL code

    roland, Feb 20, 2004
    Replies:
    1
    Views:
    939
    Andrew Beckett
    Feb 24, 2004
  4. rakesh6200

    pin display problem in autoLayout

    rakesh6200, Feb 24, 2004
    Replies:
    0
    Views:
    634
    rakesh6200
    Feb 24, 2004
  5. Shanthi Pavan

    Lookup Table in Verilog-A

    Shanthi Pavan, Feb 23, 2004
    Replies:
    1
    Views:
    2,340
    Andrew Beckett
    Feb 23, 2004
  6. Thuong

    Dracula's WID command

    Thuong, Feb 18, 2004
    Replies:
    1
    Views:
    793
    Andrew Beckett
    Feb 23, 2004
  7. cupric

    Obtaining small signal conductance

    cupric, Feb 23, 2004
    Replies:
    2
    Views:
    696
    cupric
    Feb 23, 2004
  8. Fritz Lange

    way to export a small time span of a big transient simulation in spectre ?

    Fritz Lange, Feb 23, 2004
    Replies:
    1
    Views:
    845
    S. Badel
    Feb 23, 2004
  9. Kuan Zhou

    Parametric Analysis

    Kuan Zhou, Feb 21, 2004
    Replies:
    1
    Views:
    650
    S. Badel
    Feb 23, 2004
  10. boki

    Whatever I layout, the Calibre LVS always pass....

    boki, Feb 22, 2004
    Replies:
    0
    Views:
    954
    boki
    Feb 22, 2004
  11. Simon S. IBM

    Random logic verilog gate netlist generator

    Simon S. IBM, Feb 14, 2004
    Replies:
    3
    Views:
    1,254
    B. Joshua Rosen
    Feb 21, 2004
  12. Erik Wanta

    standard symbol size?

    Erik Wanta, Feb 16, 2004
    Replies:
    1
    Views:
    1,066
    John Gianni
    Feb 21, 2004
  13. compact

    Verilog-A vector syntax

    compact, Feb 20, 2004
    Replies:
    0
    Views:
    935
    compact
    Feb 20, 2004
  14. jools

    Cell Layout creation from Standard Cells

    jools, Feb 19, 2004
    Replies:
    3
    Views:
    1,003
    jools
    Feb 20, 2004
  15. tritue

    Silicon ensemble delay extraction

    tritue, Feb 19, 2004
    Replies:
    0
    Views:
    726
    tritue
    Feb 19, 2004
  16. Riyaz

    VERILOG PLI for TCF with BuildGates & Modelsim

    Riyaz, Feb 19, 2004
    Replies:
    0
    Views:
    892
    Riyaz
    Feb 19, 2004
  17. INFO

    Invitation to Register in ISQED04

    INFO, Feb 19, 2004
    Replies:
    0
    Views:
    801
    INFO
    Feb 19, 2004
  18. Echo

    ENCOUNTER terminated by internal (SEGV) error/signal… ??

    Echo, Feb 19, 2004
    Replies:
    0
    Views:
    2,775
    Echo
    Feb 19, 2004
  19. Chris Price

    cshunt equivalent in spectre?

    Chris Price, Feb 16, 2004
    Replies:
    2
    Views:
    886
    Chris Price
    Feb 18, 2004
  20. Echo

    what must be associated in verilog file with LEF when imported in the SOC ENCOUNTER?

    Echo, Feb 18, 2004
    Replies:
    0
    Views:
    1,080
    Echo
    Feb 18, 2004
  21. dati_remo

    Extraction of nfet and pfet

    dati_remo, Feb 11, 2004
    Replies:
    9
    Views:
    1,027
    S. Badel
    Feb 18, 2004
  22. roland

    How to setup Cadence SpectreVerilog by Skill language

    roland, Feb 17, 2004
    Replies:
    2
    Views:
    915
    roland
    Feb 18, 2004
  23. Kuan Zhou

    vcPropagateChange

    Kuan Zhou, Feb 16, 2004
    Replies:
    2
    Views:
    564
    Kuan Zhou
    Feb 18, 2004
  24. boki

    A high speed switch?

    boki, Feb 17, 2004
    Replies:
    2
    Views:
    864
    boki
    Feb 18, 2004
  25. smartchi

    n2port PSS simulation.

    smartchi, Feb 17, 2004
    Replies:
    1
    Views:
    1,232
    Andrew Beckett
    Feb 17, 2004
  26. Erik Wanta

    trigger SKILL on copy from library manager

    Erik Wanta, Jan 15, 2004
    Replies:
    8
    Views:
    1,058
    Erik Wanta
    Feb 17, 2004
  27. Fritz Lange

    Problems to view log files in JobMonitor

    Fritz Lange, Feb 12, 2004
    Replies:
    2
    Views:
    686
    Fritz Lange
    Feb 16, 2004
  28. Ntfs

    Different Results between Unix Cadence 4.46 and Linux Cadence 5.032

    Ntfs, Feb 10, 2004
    Replies:
    1
    Views:
    1,011
    Erik Wanta
    Feb 16, 2004
  29. Kuan Zhou

    How to generate 32 bit random binrary inputs

    Kuan Zhou, Feb 13, 2004
    Replies:
    1
    Views:
    820
    Erik Wanta
    Feb 16, 2004
  30. Echo

    why the abstract can't creat boundary?

    Echo, Feb 15, 2004
    Replies:
    0
    Views:
    898
    Echo
    Feb 15, 2004
  31. Sepe Susi

    Diva DRC/Extract >10 times faster with small blocks

    Sepe Susi, Feb 12, 2004
    Replies:
    6
    Views:
    932
    Diva Physical Verification
    Feb 13, 2004
  32. Erik Wanta

    get pointer to data in SKILL?

    Erik Wanta, Feb 13, 2004
    Replies:
    1
    Views:
    1,212
    Andrew Beckett
    Feb 13, 2004
  33. Umut Arslan

    Using Spice Macromodels in Cadence

    Umut Arslan, Feb 9, 2004
    Replies:
    1
    Views:
    786
    Andrew Beckett
    Feb 13, 2004
  34. cupric

    state space based circuit simulator

    cupric, Feb 13, 2004
    Replies:
    0
    Views:
    684
    cupric
    Feb 13, 2004
  35. Sa

    UserLevelCDFs-ITKDB

    Sa, Feb 6, 2004
    Replies:
    1
    Views:
    806
    Andrew Beckett
    Feb 13, 2004
  36. weidongl

    Skill Q: Create a label in a symbolView

    weidongl, Feb 13, 2004
    Replies:
    1
    Views:
    926
    weidongl
    Feb 13, 2004
  37. Chi-Hong, CHAN

    About ASSURA and HIT-KIT 3.40

    Chi-Hong, CHAN, Feb 12, 2004
    Replies:
    2
    Views:
    876
    [email protected]
    Feb 13, 2004
  38. solmaz

    creating technology file (introducing a new technology)

    solmaz, Feb 10, 2004
    Replies:
    4
    Views:
    1,320
    fogh
    Feb 12, 2004
  39. BRAHmS

    IP suppiler

    BRAHmS, Feb 12, 2004
    Replies:
    0
    Views:
    522
    BRAHmS
    Feb 12, 2004
  40. Raymond

    Pin Name Problem in Assura

    Raymond, Feb 12, 2004
    Replies:
    1
    Views:
    767
    Kholdoun TORKI
    Feb 12, 2004
  41. Jon Eberhardt

    Cad Technician currently available for subcontract (offsite/telecommuting) CAD drafting/design.

    Jon Eberhardt, Feb 12, 2004
    Replies:
    0
    Views:
    1,123
    Jon Eberhardt
    Feb 12, 2004
  42. Mike Russell

    inherited connections & diva parasitics

    Mike Russell, Feb 11, 2004
    Replies:
    1
    Views:
    932
    Diva Physical Verification
    Feb 12, 2004
  43. Jimmy Blue

    Pushing simulator session variables into veriloga models?

    Jimmy Blue, Feb 9, 2004
    Replies:
    2
    Views:
    964
    Andrew Beckett
    Feb 11, 2004
  44. kirit valia

    Help with PowerMill

    kirit valia, Feb 10, 2004
    Replies:
    0
    Views:
    666
    kirit valia
    Feb 10, 2004
  45. Christoph Piotrowski

    BuildGates5 LPS using TCF file

    Christoph Piotrowski, Feb 10, 2004
    Replies:
    1
    Views:
    795
    Johannes Wolkerstorfer
    Feb 10, 2004
  46. fogh

    CMI and custom C code

    fogh, Feb 10, 2004
    Replies:
    0
    Views:
    912
    fogh
    Feb 10, 2004
  47. Ed Nowak

    Orcad Pspice Analog circuit problem

    Ed Nowak, Feb 6, 2004
    Replies:
    1
    Views:
    897
    Tim Roy
    Feb 10, 2004
  48. Erik Wanta

    Cadence library encryption?

    Erik Wanta, Feb 4, 2004
    Replies:
    4
    Views:
    1,250
    fogh
    Feb 10, 2004
  49. Bernd Fischer

    SKILL Q: How to get a hir prop forn the tch lib?

    Bernd Fischer, Feb 10, 2004
    Replies:
    4
    Views:
    943
    Bernd Fischer
    Feb 10, 2004
  50. selvakumar_in

    creating .lib file ?

    selvakumar_in, Feb 10, 2004
    Replies:
    0
    Views:
    686
    [email protected]
    Feb 10, 2004
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