Cadence

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  1. ARAVIND

    verilog to schematic problem.

    ARAVIND, Jun 15, 2004
    Replies:
    1
    Views:
    1,195
    Bernd Fischer
    Jun 15, 2004
  2. aditya

    pcellEvalFailed

    aditya, Jun 12, 2004
    Replies:
    1
    Views:
    725
    aditya
    Jun 12, 2004
  3. Jimmy Blue

    How to get VS off my design libraries?

    Jimmy Blue, May 28, 2004
    Replies:
    2
    Views:
    729
    mRbONK
    Jun 12, 2004
  4. Hon Seng Phuah

    OK and Cancel buttons callback

    Hon Seng Phuah, Jun 11, 2004
    Replies:
    3
    Views:
    1,012
    Jim Newton
    Jun 11, 2004
  5. S. Badel

    saving custom data into artist states?

    S. Badel, Jun 3, 2004
    Replies:
    2
    Views:
    1,212
    Erik Wanta
    Jun 10, 2004
  6. Mark Holland

    Virtuoso Compactor Rules for tsmc .18 native

    Mark Holland, Jun 10, 2004
    Replies:
    0
    Views:
    1,234
    Mark Holland
    Jun 10, 2004
  7. Jan Mikkelsen

    Monte-Carlo simulations

    Jan Mikkelsen, Jun 9, 2004
    Replies:
    1
    Views:
    979
    Andrew Beckett
    Jun 9, 2004
  8. Manju Arasaiah

    Assura question on density checking

    Manju Arasaiah, Jun 4, 2004
    Replies:
    1
    Views:
    1,314
    Jay Lessert
    Jun 8, 2004
  9. Randy

    CAD Comparison

    Randy, Jun 8, 2004
    Replies:
    0
    Views:
    749
    Randy
    Jun 8, 2004
  10. Manju Arasaiah

    Assura's dot files in the current directory -creates issues with multiple users...

    Manju Arasaiah, Jun 3, 2004
    Replies:
    7
    Views:
    981
    Manju Arasaiah
    Jun 8, 2004
  11. Thomas Popp

    HDL Simulator and Current Simulation

    Thomas Popp, Jun 7, 2004
    Replies:
    0
    Views:
    734
    Thomas Popp
    Jun 7, 2004
  12. Kuan Zhou

    How to specify DRC tempory directory

    Kuan Zhou, Jun 4, 2004
    Replies:
    2
    Views:
    849
    Diva Physical Verification
    Jun 5, 2004
  13. Andrey Orlenko 395924625

    dbTransformCellView

    Andrey Orlenko 395924625, Jun 3, 2004
    Replies:
    1
    Views:
    940
    Andrew Beckett
    Jun 3, 2004
  14. Fritz Lange

    Generate X versus Y plot with OCEAN or Skill (example Eyediagram)

    Fritz Lange, May 14, 2004
    Replies:
    4
    Views:
    1,134
    Andrew Beckett
    Jun 3, 2004
  15. Ercan Altuntas

    *Error* eval: undefined function - proc

    Ercan Altuntas, May 25, 2004
    Replies:
    8
    Views:
    1,882
    Andrew Beckett
    Jun 3, 2004
  16. Alexey Borodenkov

    Plots to file from schematic editor

    Alexey Borodenkov, Apr 26, 2004 ... 2
    Replies:
    25
    Views:
    2,724
    Andrew Beckett
    Jun 3, 2004
  17. RobertG

    beginner's few problems

    RobertG, May 28, 2004
    Replies:
    1
    Views:
    862
    Andrew Beckett
    Jun 3, 2004
  18. Juvezio

    How do run Spectre on Multiple CPU?

    Juvezio, May 27, 2004
    Replies:
    1
    Views:
    1,048
    Andrew Beckett
    Jun 3, 2004
  19. Mircea Gindila

    Variable capacitance model

    Mircea Gindila, Jun 1, 2004
    Replies:
    1
    Views:
    662
    Andrew Beckett
    Jun 3, 2004
  20. Juan Felipe Osorio

    save signals from a big extracted view.

    Juan Felipe Osorio, Jun 1, 2004
    Replies:
    0
    Views:
    846
    Juan Felipe Osorio
    Jun 1, 2004
  21. CADPROGRAMMS

    programmms for engineers

    CADPROGRAMMS, Jun 1, 2004
    Replies:
    0
    Views:
    633
    CADPROGRAMMS
    Jun 1, 2004
  22. jools

    LVS and terminal mapping

    jools, May 30, 2004
    Replies:
    2
    Views:
    892
    S. Badel
    May 31, 2004
  23. yogesh

    what is the meaning of CAE and CIM?

    yogesh, May 14, 2004
    Replies:
    5
    Views:
    799
    Doug Dingus
    May 30, 2004
  24. Jim Newton

    why is SKILL++ not very popular

    Jim Newton, May 29, 2004
    Replies:
    0
    Views:
    618
    Jim Newton
    May 29, 2004
  25. Erik Wanta

    IC Installation $PATH?

    Erik Wanta, May 23, 2004
    Replies:
    3
    Views:
    909
    John Gianni
    May 28, 2004
  26. Shumble

    LSW Window

    Shumble, May 26, 2004
    Replies:
    5
    Views:
    1,056
    G Vandevalk
    May 27, 2004
  27. Harald Neubauer

    OpenMosix or Gridengine experience

    Harald Neubauer, May 26, 2004
    Replies:
    5
    Views:
    753
    Andrew Beckett
    May 27, 2004
  28. BL

    Run Verilog-XL error in IC5.0

    BL, May 21, 2004
    Replies:
    3
    Views:
    650
    Andrew Beckett
    May 27, 2004
  29. HDL Book Seller

    Looking for top Verilog, VHDL reference texts?

    HDL Book Seller, May 27, 2004
    Replies:
    0
    Views:
    826
    HDL Book Seller
    May 27, 2004
  30. Jerry Bires

    Bangalore-based ASIC/CAD Tech Lead, Parasitic Extraction

    Jerry Bires, May 26, 2004
    Replies:
    0
    Views:
    953
    Jerry Bires
    May 26, 2004
  31. Jerry Bires

    Bangalore-based SoC Wireless Design Manager

    Jerry Bires, May 26, 2004
    Replies:
    0
    Views:
    1,014
    Jerry Bires
    May 26, 2004
  32. Guneet Singh

    AMS simulation

    Guneet Singh, May 25, 2004
    Replies:
    4
    Views:
    1,549
    Guneet Singh
    May 26, 2004
  33. Shumble

    LSW Window in 4.4.6

    Shumble, May 26, 2004
    Replies:
    1
    Views:
    723
    @adewilde.tmfweb.nl@SPAMBLOCK
    May 26, 2004
  34. Alexey Borodenkov

    transistor noise in TRAN simulation

    Alexey Borodenkov, May 24, 2004
    Replies:
    4
    Views:
    1,028
    Paul Muller
    May 26, 2004
  35. Chander

    Regarding Analog Environment of Cadence + Simulation

    Chander, May 19, 2004
    Replies:
    2
    Views:
    905
    John Gianni
    May 26, 2004
  36. New User ^_^

    Schematic Pins

    New User ^_^, May 19, 2004
    Replies:
    2
    Views:
    921
    Andrew Beckett
    May 25, 2004
  37. Stephane Mazurie

    CADENCE Noise analysis

    Stephane Mazurie, May 15, 2004
    Replies:
    3
    Views:
    1,116
    Andrew Beckett
    May 25, 2004
  38. yogesh

    scenario before parametric design concept..

    yogesh, May 21, 2004
    Replies:
    4
    Views:
    774
    yogesh
    May 24, 2004
  39. Raf

    Suppress dialog boxes ...

    Raf, May 19, 2004
    Replies:
    1
    Views:
    978
    Andrew Beckett
    May 20, 2004
  40. S. Badel

    Assura post-layout sim with standard cells

    S. Badel, May 19, 2004
    Replies:
    1
    Views:
    1,011
    Erik Wanta
    May 20, 2004
  41. Kuan Zhou

    Is Cadence Expensive?

    Kuan Zhou, May 11, 2004
    Replies:
    7
    Views:
    847
    Andrew Beckett
    May 19, 2004
  42. Fritz Lange

    Redirect Output in CIW when launching OCEAN skript

    Fritz Lange, May 18, 2004
    Replies:
    1
    Views:
    840
    Andrew Beckett
    May 19, 2004
  43. BL

    LVS error

    BL, May 18, 2004
    Replies:
    1
    Views:
    1,361
    Diva Physical Verification
    May 19, 2004
  44. J M

    Problem with Simulation

    J M, May 4, 2004
    Replies:
    4
    Views:
    769
    Chander
    May 18, 2004
  45. New User ^_^

    Question on Symbol Selection Box

    New User ^_^, May 18, 2004
    Replies:
    1
    Views:
    629
    S. Badel
    May 18, 2004
  46. Fred Ma

    Simple way to generate random netlists of ALU cells

    Fred Ma, May 14, 2004
    Replies:
    9
    Views:
    1,074
    Fred Ma
    May 18, 2004
  47. Prasanna Tamhankar

    create schematic from netlist ?

    Prasanna Tamhankar, May 13, 2004
    Replies:
    2
    Views:
    1,059
    Simon S. IBM
    May 16, 2004
  48. Kuan Zhou

    Spectre simulation problem

    Kuan Zhou, Apr 19, 2004
    Replies:
    3
    Views:
    869
    Kuan Zhou
    May 16, 2004
  49. Moises Paniagua

    LVS

    Moises Paniagua, May 16, 2004
    Replies:
    0
    Views:
    716
    Moises Paniagua
    May 16, 2004
  50. Fred Ma

    MCNC benchmarks (was: Simple way to generate random netlists of ALUcells)

    Fred Ma, May 15, 2004
    Replies:
    0
    Views:
    857
    Fred Ma
    May 15, 2004
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