Cadence

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  1. Manju Arasaiah

    How to get TOPCELLNAME from a GDS file without opening any GUI?

    Manju Arasaiah, Jun 25, 2004
    Replies:
    14
    Views:
    1,420
    Kholdoun TORKI
    Aug 24, 2004
  2. Ercan Altuntas

    netlistProcedure Help

    Ercan Altuntas, Aug 10, 2004
    Replies:
    7
    Views:
    690
    Ercan Altuntas
    Aug 24, 2004
  3. Spaceghost

    Vias not extracting

    Spaceghost, Aug 21, 2004
    Replies:
    2
    Views:
    656
    Spaceghost
    Aug 23, 2004
  4. Martin Lefebvre

    Spectre hostname problem

    Martin Lefebvre, Aug 12, 2004
    Replies:
    2
    Views:
    658
    DaDeXTeR
    Aug 21, 2004
  5. Suresh Jeevanandam

    Getting the first n elements from a list

    Suresh Jeevanandam, Aug 19, 2004
    Replies:
    3
    Views:
    1,110
    Suresh Jeevanandam
    Aug 20, 2004
  6. Frank Nitsche

    noise analysis of a time discrete system (SC-amplifier)

    Frank Nitsche, Aug 19, 2004
    Replies:
    3
    Views:
    888
    Andrew Beckett
    Aug 20, 2004
  7. Sylvio Triebel

    Artist Calculator expressions <--> Ocean

    Sylvio Triebel, Aug 19, 2004
    Replies:
    2
    Views:
    885
    Sylvio Triebel
    Aug 20, 2004
  8. Jackson Harvey

    Recognizing SKILL based layouts?

    Jackson Harvey, Aug 19, 2004
    Replies:
    1
    Views:
    680
    Andrew Beckett
    Aug 19, 2004
  9. svenn.are

    More about file locking in cadence

    svenn.are, Aug 19, 2004
    Replies:
    1
    Views:
    974
    Andrew Beckett
    Aug 19, 2004
  10. ÎâÆóÖÜ\(sanguine\)

    Spectre simulation question

    ÎâÆóÖÜ\(sanguine\), Aug 12, 2004
    Replies:
    4
    Views:
    2,641
    Andrew Beckett
    Aug 19, 2004
  11. fogh

    spectre conditional models

    fogh, Aug 5, 2004
    Replies:
    4
    Views:
    863
    Andrew Beckett
    Aug 19, 2004
  12. Matt

    forms pausing SKILL execution

    Matt, Aug 17, 2004
    Replies:
    1
    Views:
    992
    Andrew Beckett
    Aug 19, 2004
  13. Nadine

    How to get gm during a transient analysis?

    Nadine, Aug 18, 2004
    Replies:
    3
    Views:
    866
    Andrew Beckett
    Aug 19, 2004
  14. Kumar Yelamarthi

    Display signals in hex format in Spectre

    Kumar Yelamarthi, Aug 18, 2004
    Replies:
    1
    Views:
    772
    A. B.
    Aug 18, 2004
  15. tnk

    bus bits problem <> [ ]

    tnk, Aug 18, 2004
    Replies:
    0
    Views:
    1,092
    tnk
    Aug 18, 2004
  16. George

    why 0.35um instead of 0.6um???

    George, Aug 17, 2004
    Replies:
    2
    Views:
    675
    George
    Aug 18, 2004
  17. kumi

    cadence help

    kumi, Aug 17, 2004
    Replies:
    0
    Views:
    610
    kumi
    Aug 17, 2004
  18. Kholdoun TORKI

    IEEE ICM'2004 Extended Call For Papers

    Kholdoun TORKI, Aug 17, 2004
    Replies:
    0
    Views:
    884
    Kholdoun TORKI
    Aug 17, 2004
  19. Lee

    Verification for a big chip???

    Lee, Aug 12, 2004
    Replies:
    1
    Views:
    632
    Karl Fritz
    Aug 17, 2004
  20. Karl Fritz

    replace symbolic vias with layout vias in Virtuoso?

    Karl Fritz, Aug 16, 2004
    Replies:
    3
    Views:
    1,301
    Karl Fritz
    Aug 17, 2004
  21. Stefan Joeres

    Java-Problems with IC5.0.33/IC5.10.41

    Stefan Joeres, Aug 17, 2004
    Replies:
    0
    Views:
    946
    Stefan Joeres
    Aug 17, 2004
  22. info

    CALL FOR PAPERS, IEEE ISQED05

    info, Aug 15, 2004
    Replies:
    0
    Views:
    803
    info
    Aug 15, 2004
  23. Matt

    Virtuoso Custom Placer (VCP) question

    Matt, Aug 13, 2004
    Replies:
    0
    Views:
    1,093
    Matt
    Aug 13, 2004
  24. svenn.are

    Reading data into veriloga testbench from file

    svenn.are, Aug 10, 2004
    Replies:
    1
    Views:
    2,249
    Andrew Beckett
    Aug 13, 2004
  25. harry

    Why my timing parametrs don't show up in my verilog netlist

    harry, Aug 5, 2004
    Replies:
    4
    Views:
    906
    Andrew Beckett
    Aug 13, 2004
  26. Shaun Johnson

    No properties when instance queried

    Shaun Johnson, Aug 10, 2004
    Replies:
    2
    Views:
    645
    Andrew Beckett
    Aug 13, 2004
  27. Lee

    Solve the DRC error in Cadence???

    Lee, Aug 5, 2004
    Replies:
    9
    Views:
    1,471
    harry
    Aug 13, 2004
  28. Jan Mikkelsen

    Using 'path' gives off-grid errors

    Jan Mikkelsen, Aug 11, 2004
    Replies:
    4
    Views:
    1,234
    G Vandevalk
    Aug 12, 2004
  29. Nikolaos Kasparidis

    hiCreateTabField

    Nikolaos Kasparidis, Aug 10, 2004
    Replies:
    2
    Views:
    633
    Nikolaos Kasparidis
    Aug 11, 2004
  30. Nikolaos Kasparidis

    hiCreateTabField

    Nikolaos Kasparidis, Aug 10, 2004
    Replies:
    0
    Views:
    705
    Nikolaos Kasparidis
    Aug 10, 2004
  31. rajan

    Back Annotation simulations

    rajan, Aug 7, 2004
    Replies:
    3
    Views:
    1,136
    Ansgar Bambynek
    Aug 10, 2004
  32. Jason D. Bakos

    Global nets

    Jason D. Bakos, Aug 9, 2004
    Replies:
    1
    Views:
    827
    Andrew Beckett
    Aug 10, 2004
  33. Peter Wilson

    how to run VHDL-AMS Simulation in Cadence

    Peter Wilson, Jul 28, 2004
    Replies:
    3
    Views:
    1,247
    Andrew Beckett
    Aug 10, 2004
  34. svenn.are

    Turn on all warnings from spectre in ade

    svenn.are, Aug 3, 2004
    Replies:
    1
    Views:
    1,760
    Andrew Beckett
    Aug 10, 2004
  35. smartchi

    Background simulation of the Spectre

    smartchi, Aug 7, 2004
    Replies:
    4
    Views:
    638
    Erik Wanta
    Aug 9, 2004
  36. Erik Wanta

    AMS Designer tcl script mode determination?

    Erik Wanta, Aug 6, 2004
    Replies:
    1
    Views:
    1,010
    Andrew Beckett
    Aug 9, 2004
  37. Lee

    Can I do LVS between gate netlist and transistor netlist in Diva?Thanks

    Lee, Aug 8, 2004
    Replies:
    1
    Views:
    1,150
    Diva Physical Verification
    Aug 8, 2004
  38. Lee

    "undefined function: avSwitch" error during LVS in Diva????

    Lee, Aug 7, 2004
    Replies:
    3
    Views:
    1,261
    Kholdoun TORKI
    Aug 8, 2004
  39. fogh

    is tools/dfII/bin/nfsUpdate really useful ?

    fogh, Aug 6, 2004
    Replies:
    1
    Views:
    831
    Andrew Beckett
    Aug 8, 2004
  40. Carson

    verilog-A

    Carson, Aug 6, 2004
    Replies:
    1
    Views:
    617
    Andrew Beckett
    Aug 8, 2004
  41. fogh

    Analog artist resize - version 1.2.3

    fogh, Aug 6, 2004
    Replies:
    0
    Views:
    959
    fogh
    Aug 6, 2004
  42. HDL Book Seller

    Bone up on VHDL & Verilog with these great reference texts at 60% off Amazon

    HDL Book Seller, Aug 6, 2004
    Replies:
    0
    Views:
    837
    HDL Book Seller
    Aug 6, 2004
  43. Lee

    Back-annotation for PrimeTime and power compiler in Synopsys by using Cadebce tools???

    Lee, Aug 6, 2004
    Replies:
    0
    Views:
    1,077
    Lee
    Aug 6, 2004
  44. Bob Moore

    mouseAddPt() force

    Bob Moore, Aug 3, 2004 ... 2
    Replies:
    23
    Views:
    2,119
    Bob Moore
    Aug 6, 2004
  45. Lee

    DRC in Virtuoso????

    Lee, Aug 2, 2004
    Replies:
    5
    Views:
    866
    Diva Physical Verification
    Aug 5, 2004
  46. Suresh Jeevanandam

    Swapping the rows and columns in a two dimensional array

    Suresh Jeevanandam, Aug 4, 2004
    Replies:
    4
    Views:
    1,145
    Satya Mishra
    Aug 5, 2004
  47. Thethys

    Gilbert cell Mixer : differential or single-ended?

    Thethys, Aug 4, 2004
    Replies:
    1
    Views:
    1,095
    fogh
    Aug 5, 2004
  48. Spaceghost

    Parameterized Schematic Instances?

    Spaceghost, Jul 31, 2004
    Replies:
    7
    Views:
    1,136
    fogh
    Aug 5, 2004
  49. Carson

    generate sdf

    Carson, Aug 5, 2004
    Replies:
    1
    Views:
    875
    kal
    Aug 5, 2004
  50. Suresh Jeevanandam

    Finding type of the content of a string : characters or number

    Suresh Jeevanandam, Aug 4, 2004
    Replies:
    3
    Views:
    960
    Suresh Jeevanandam
    Aug 4, 2004
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