Cadence

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  1. Manivannan

    using Zero Order Hold in Cadence

    Manivannan, Sep 20, 2004
    Replies:
    0
    Views:
    986
    Manivannan
    Sep 20, 2004
  2. vipan

    clock root in synthesis

    vipan, Sep 20, 2004
    Replies:
    0
    Views:
    955
    vipan
    Sep 20, 2004
  3. Rajeswaran M

    Library Manager Fails to invoke!

    Rajeswaran M, Sep 20, 2004
    Replies:
    0
    Views:
    1,189
    Rajeswaran M
    Sep 20, 2004
  4. sam

    missing options in hardCopyOptions()?

    sam, Sep 17, 2004
    Replies:
    1
    Views:
    664
    Andrew Beckett
    Sep 20, 2004
  5. Jan Beck

    Problems with Ground plane artwork

    Jan Beck, Sep 16, 2004
    Replies:
    3
    Views:
    770
    Jan Beck
    Sep 19, 2004
  6. rajan

    Insertion delay

    rajan, Sep 17, 2004
    Replies:
    1
    Views:
    730
    Mike Treseler
    Sep 18, 2004
  7. Suresh Jeevanandam

    Virtuoso XL: Having two separate libraries for layout and schematic

    Suresh Jeevanandam, Sep 15, 2004
    Replies:
    5
    Views:
    1,230
    Suresh Jeevanandam
    Sep 17, 2004
  8. tritue truong

    Monte carlo model for matching

    tritue truong, Sep 7, 2004
    Replies:
    2
    Views:
    897
    fogh
    Sep 16, 2004
  9. Suresh Jeevanandam

    Bindkeys

    Suresh Jeevanandam, Sep 16, 2004
    Replies:
    0
    Views:
    846
    Suresh Jeevanandam
    Sep 16, 2004
  10. David Witkowski

    ICU2004: SKILL SIG, OpenSKILL Initiative

    David Witkowski, Aug 24, 2004
    Replies:
    2
    Views:
    622
    fogh
    Sep 16, 2004
  11. rajan

    synthesis

    rajan, Sep 14, 2004
    Replies:
    0
    Views:
    742
    rajan
    Sep 14, 2004
  12. rajan

    synthesis script

    rajan, Sep 14, 2004
    Replies:
    0
    Views:
    720
    rajan
    Sep 14, 2004
  13. Martin Feldhofer

    I/O pin placement

    Martin Feldhofer, Sep 14, 2004
    Replies:
    0
    Views:
    729
    Martin Feldhofer
    Sep 14, 2004
  14. Erik Wanta

    *FATAL* voFree

    Erik Wanta, Sep 14, 2004
    Replies:
    2
    Views:
    523
    Andrew Beckett
    Sep 14, 2004
  15. Riaz

    mapping vector names to flat netlist nodes

    Riaz, Sep 12, 2004
    Replies:
    1
    Views:
    914
    Andrew Beckett
    Sep 13, 2004
  16. Erik Wanta

    2 function bindkey unfuctional in IC5141?

    Erik Wanta, Sep 2, 2004
    Replies:
    6
    Views:
    1,051
    Andrew Beckett
    Sep 13, 2004
  17. Frank Nitsche

    How to load saved waveform window back into awd without using filedialogue window?

    Frank Nitsche, Sep 7, 2004
    Replies:
    2
    Views:
    1,179
    Frank Nitsche
    Sep 13, 2004
  18. MOSripper

    converting Hspice tech file to spectre tech file

    MOSripper, Sep 10, 2004
    Replies:
    2
    Views:
    1,059
    MOSripper
    Sep 12, 2004
  19. Suresh Jeevanandam

    Processing connectivity in a schematic

    Suresh Jeevanandam, Sep 10, 2004
    Replies:
    0
    Views:
    666
    Suresh Jeevanandam
    Sep 10, 2004
  20. cadence_newbie

    Pcell stretch line default value.

    cadence_newbie, Sep 7, 2004
    Replies:
    1
    Views:
    841
    Andrew Beckett
    Sep 9, 2004
  21. Jan Hovius

    What does cdsMsgServer do exactly and is there an easy way to kill it after exiting cadence?

    Jan Hovius, Jul 14, 2004
    Replies:
    10
    Views:
    1,364
    Andrew Beckett
    Sep 9, 2004
  22. JonDole

    Using 2-port parameters in simulation (possible?).

    JonDole, Sep 9, 2004
    Replies:
    2
    Views:
    732
    Andrew Beckett
    Sep 9, 2004
  23. Jan Hovius

    Is it possible to plot the fundamental frequency vs. tuning voltage in swept pss analysis?

    Jan Hovius, Sep 7, 2004
    Replies:
    1
    Views:
    1,074
    Andrew Beckett
    Sep 9, 2004
  24. leak

    Need Convert DWG/DXF to BMP ,GIF,JPG, EMF, or PDF ???

    leak, Sep 7, 2004
    Replies:
    0
    Views:
    966
    leak
    Sep 7, 2004
  25. Bernd Fischer

    Assura file locking

    Bernd Fischer, Sep 3, 2004
    Replies:
    2
    Views:
    902
    Bernd Fischer
    Sep 6, 2004
  26. Kholdoun TORKI

    IEEE ICM'2004 last Call For Papers

    Kholdoun TORKI, Sep 4, 2004
    Replies:
    0
    Views:
    842
    Kholdoun TORKI
    Sep 4, 2004
  27. Henrik Johansson

    IPC problems

    Henrik Johansson, Sep 2, 2004
    Replies:
    3
    Views:
    893
    Erik Wanta
    Sep 4, 2004
  28. Jay Smith

    Assura RCX error: *FATAL* at "rex": res command file error - imcomplete ???

    Jay Smith, Aug 30, 2004
    Replies:
    5
    Views:
    1,346
    Erik Wanta
    Sep 3, 2004
  29. tnk

    macro lvs

    tnk, Sep 2, 2004
    Replies:
    3
    Views:
    741
    Andrew Beckett
    Sep 3, 2004
  30. Newer

    help: capture generates netlist to allegro

    Newer, Sep 3, 2004
    Replies:
    0
    Views:
    1,244
    Newer
    Sep 3, 2004
  31. Frank Nitsche

    equivalent skill function to schPlot for awd waveform window

    Frank Nitsche, Aug 31, 2004
    Replies:
    2
    Views:
    911
    Frank Nitsche
    Sep 2, 2004
  32. rajan

    synthesis error with DC

    rajan, Aug 30, 2004
    Replies:
    2
    Views:
    870
    Metin Yerlikaya
    Sep 1, 2004
  33. rajan

    assign statement in netlist

    rajan, Aug 26, 2004
    Replies:
    4
    Views:
    829
    Kholdoun TORKI
    Sep 1, 2004
  34. Nikolaos Kasparidis

    hiCreateCyclicField dimension

    Nikolaos Kasparidis, Aug 31, 2004
    Replies:
    2
    Views:
    716
    Pete nospam Zakel
    Aug 31, 2004
  35. HDL Book Seller

    Verilog & VHDL reference texts

    HDL Book Seller, Aug 31, 2004
    Replies:
    0
    Views:
    785
    HDL Book Seller
    Aug 31, 2004
  36. Oskar Drugge

    Greek Prefixes with fprintf

    Oskar Drugge, Aug 31, 2004
    Replies:
    1
    Views:
    745
    Andrew Beckett
    Aug 31, 2004
  37. Carl Cursujani

    Log Files in Job Monitor are not shown because they are stored inthe local temp folder

    Carl Cursujani, Aug 25, 2004
    Replies:
    4
    Views:
    1,179
    Andrew Beckett
    Aug 31, 2004
  38. Carl Cursujani

    Problems to delete simulation results under Cadence Analog DesignEnvironement

    Carl Cursujani, Aug 19, 2004
    Replies:
    6
    Views:
    1,243
    Andrew Beckett
    Aug 31, 2004
  39. Steve Hamm

    Specify-VerilogXL

    Steve Hamm, Aug 30, 2004
    Replies:
    0
    Views:
    731
    Steve Hamm
    Aug 30, 2004
  40. Carl Cursujani

    Which Cadence version is needed to use asimenv.distributed deleteJobOption

    Carl Cursujani, Aug 25, 2004
    Replies:
    1
    Views:
    807
    Erik Wanta
    Aug 29, 2004
  41. Ronald

    Looking for example OpenAccess technology file for Opus library

    Ronald, Aug 12, 2004
    Replies:
    2
    Views:
    1,312
    John Gianni
    Aug 27, 2004
  42. Debbie Unger

    is NCSU_CDK.1.3 technology file compatible with cadence 5.0.33

    Debbie Unger, Aug 27, 2004
    Replies:
    0
    Views:
    756
    Debbie Unger
    Aug 27, 2004
  43. Debbie Unger

    cadence technology file

    Debbie Unger, Aug 27, 2004
    Replies:
    0
    Views:
    694
    Debbie Unger
    Aug 27, 2004
  44. Lee

    Chip Assembly and Pad Assembly in ICC???

    Lee, Aug 9, 2004
    Replies:
    1
    Views:
    939
    Debbie Unger
    Aug 27, 2004
  45. Rajeswaran M

    Flat Verilog netlist - out

    Rajeswaran M, Aug 11, 2004
    Replies:
    1
    Views:
    907
    Debbie Unger
    Aug 27, 2004
  46. Tracy Groller

    leSearchHierarchy

    Tracy Groller, Aug 25, 2004
    Replies:
    3
    Views:
    644
    Andrew Beckett
    Aug 26, 2004
  47. Manivannan

    runnig vhdl-ams

    Manivannan, Aug 24, 2004
    Replies:
    4
    Views:
    846
    Rajeswaran M
    Aug 26, 2004
  48. Rick

    loading DFII keyboard into CCAR/ICCraftsman

    Rick, Aug 25, 2004
    Replies:
    1
    Views:
    677
    A. B.
    Aug 25, 2004
  49. Erik Wanta

    awd = wavescan??

    Erik Wanta, Aug 23, 2004
    Replies:
    2
    Views:
    1,002
    Robert Schopmeyer
    Aug 24, 2004
  50. Pankaj Golani

    Silicon Emsemble

    Pankaj Golani, Aug 24, 2004
    Replies:
    0
    Views:
    466
    Pankaj Golani
    Aug 24, 2004
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