Cadence

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  1. Aby

    Edge Not on Grid

    Aby, May 13, 2005
    Replies:
    2
    Views:
    1,197
    G Vandevalk
    May 13, 2005
  2. stroller

    composer schematics / virtuoso layout editor support on mac osX

    stroller, Apr 28, 2005
    Replies:
    6
    Views:
    1,014
    David Cuthbert
    May 12, 2005
  3. janbeck

    Via Within pad for SMD caps and resistors

    janbeck, May 12, 2005
    Replies:
    1
    Views:
    879
    [email protected]
    May 12, 2005
  4. Stefan Joeres

    Tutorial implementing Skill-Tools

    Stefan Joeres, May 11, 2005
    Replies:
    2
    Views:
    790
    S. Badel
    May 12, 2005
  5. Heidi

    A free graphical netlist trace and modification tool

    Heidi, May 11, 2005
    Replies:
    1
    Views:
    910
    [email protected]
    May 12, 2005
  6. Raf Karakiewicz

    change reference library of SOME cells

    Raf Karakiewicz, May 10, 2005
    Replies:
    2
    Views:
    690
    Raf Karakiewicz
    May 12, 2005
  7. Seagull

    Diva Extraction

    Seagull, May 12, 2005
    Replies:
    0
    Views:
    734
    Seagull
    May 12, 2005
  8. tnk11

    spectre to hspice

    tnk11, May 11, 2005
    Replies:
    2
    Views:
    713
    [email protected]
    May 12, 2005
  9. theo

    Non Rectangular Floorplan in Silicon Ensemble

    theo, May 9, 2005
    Replies:
    2
    Views:
    685
    [email protected]
    May 11, 2005
  10. Tracy Groller

    Trigger Functions

    Tracy Groller, May 9, 2005
    Replies:
    7
    Views:
    754
    Andrew Beckett
    May 11, 2005
  11. Taha

    CMC University Program -- Tutorials

    Taha, May 10, 2005
    Replies:
    0
    Views:
    761
    Taha
    May 10, 2005
  12. Seagull

    data Input - Silicon ensemble

    Seagull, May 10, 2005
    Replies:
    1
    Views:
    617
    S. Badel
    May 10, 2005
  13. Erik Wanta

    Parent child database on Open Access

    Erik Wanta, May 10, 2005
    Replies:
    0
    Views:
    892
    Erik Wanta
    May 10, 2005
  14. David Chinn

    Question about : Upgrade from DFII4.46 -> 5.xx

    David Chinn, May 9, 2005
    Replies:
    2
    Views:
    863
    John Gianni
    May 9, 2005
  15. Roland.Fontaine

    creating string containing quotes (" ")

    Roland.Fontaine, May 9, 2005
    Replies:
    4
    Views:
    699
    S. Badel
    May 9, 2005
  16. Svenn Are Bjerkem

    transmission line as verilog-a or spectre-HDL

    Svenn Are Bjerkem, May 9, 2005
    Replies:
    2
    Views:
    760
    Andrew Beckett
    May 9, 2005
  17. Svenn Are Bjerkem

    cyclic fields and spectreHDL

    Svenn Are Bjerkem, May 4, 2005
    Replies:
    2
    Views:
    790
    Svenn Are Bjerkem
    May 9, 2005
  18. eda_cadence

    how to capture demosondemand videos

    eda_cadence, May 1, 2005
    Replies:
    5
    Views:
    719
    eda_cadence
    May 6, 2005
  19. kimo

    OA version vs CDB

    kimo, May 4, 2005
    Replies:
    4
    Views:
    1,481
    John Gianni
    May 5, 2005
  20. eda_cadence

    pks help in adding power stripes

    eda_cadence, May 5, 2005
    Replies:
    3
    Views:
    623
    mk
    May 5, 2005
  21. Bernd Fischer

    GDSII merge

    Bernd Fischer, May 2, 2005
    Replies:
    3
    Views:
    795
    [email protected]
    May 4, 2005
  22. danmc

    versionsync vs command line netlisting

    danmc, May 3, 2005
    Replies:
    1
    Views:
    702
    Andrew Beckett
    May 4, 2005
  23. chloe_music2003

    Reload Verilog file in SimVision

    chloe_music2003, Apr 22, 2005
    Replies:
    6
    Views:
    1,448
    [email protected]
    May 4, 2005
  24. Chris

    Memory Leak in LDV 4.1 and 5.1 when using Restart?

    Chris, May 3, 2005
    Replies:
    0
    Views:
    875
    Chris
    May 3, 2005
  25. Bernd Fischer

    AWD and SST2

    Bernd Fischer, Apr 19, 2005
    Replies:
    1
    Views:
    813
    Andrew Beckett
    May 3, 2005
  26. pureck

    loadpull simulation for PA

    pureck, Apr 27, 2005
    Replies:
    1
    Views:
    570
    Andrew Beckett
    May 3, 2005
  27. Kuan Zhou

    Cadence tool suggestion

    Kuan Zhou, Apr 27, 2005
    Replies:
    2
    Views:
    653
    Andrew Beckett
    May 3, 2005
  28. Allen

    Substrate Noise Analyst

    Allen, Apr 20, 2005
    Replies:
    2
    Views:
    792
    fogh
    May 3, 2005
  29. Gunnar Munder

    Simulating Verilog-A model using spectre.

    Gunnar Munder, Apr 29, 2005
    Replies:
    2
    Views:
    864
    kvaddina
    May 2, 2005
  30. kentauta

    Virtuoso Schematic Composer: slow property window

    kentauta, Apr 14, 2005
    Replies:
    11
    Views:
    1,691
    fogh
    May 2, 2005
  31. Eric

    sedsm ctgen hierarchy problem

    Eric, May 1, 2005
    Replies:
    0
    Views:
    645
    Eric
    May 1, 2005
  32. Guenther Sohler

    Using CVS in an design enviroment

    Guenther Sohler, Apr 29, 2005
    Replies:
    4
    Views:
    710
    fogh
    May 1, 2005
  33. eda_cadence

    req:spw environmetal settings

    eda_cadence, Apr 29, 2005
    Replies:
    1
    Views:
    676
    Andrew Beckett
    Apr 29, 2005
  34. kk

    equivalent of -G for vsim in ncsim or ncverilog

    kk, Apr 28, 2005
    Replies:
    4
    Views:
    840
    kk
    Apr 29, 2005
  35. Allen

    In layout, can I put circuits under dualmim capacitor?

    Allen, Apr 26, 2005
    Replies:
    2
    Views:
    807
    G Vandevalk
    Apr 29, 2005
  36. sampah

    SKill procedure in Ocean scripts ?.

    sampah, Apr 27, 2005
    Replies:
    3
    Views:
    980
    sampah
    Apr 29, 2005
  37. kvaddina

    Simulating Verilog-A model using spectre.

    kvaddina, Apr 28, 2005
    Replies:
    1
    Views:
    1,042
    Svenn Are Bjerkem
    Apr 29, 2005
  38. Hugo Miguel Franca Santos

    Finding error in spectre

    Hugo Miguel Franca Santos, Apr 28, 2005
    Replies:
    1
    Views:
    606
    Svenn Are Bjerkem
    Apr 29, 2005
  39. Ocean D.

    Matching Circuit Design

    Ocean D., Apr 27, 2005
    Replies:
    1
    Views:
    705
    pureck
    Apr 28, 2005
  40. eda_cadence

    prob:SPW in RHEL 3

    eda_cadence, Apr 28, 2005
    Replies:
    1
    Views:
    814
    Andrew Beckett
    Apr 28, 2005
  41. amos

    which is better for you ?kakg

    amos, Apr 28, 2005
    Replies:
    0
    Views:
    954
    amos
    Apr 28, 2005
  42. Noohul Ali

    Converting synthesized VHDL/Verilog to spice netlist

    Noohul Ali, Apr 21, 2005
    Replies:
    2
    Views:
    783
    Neo
    Apr 28, 2005
  43. S.Badel

    SKILL tips for n-edit

    S.Badel, Apr 23, 2005
    Replies:
    3
    Views:
    695
    S. Badel
    Apr 28, 2005
  44. - A -

    Printing schematics in composer!!

    - A -, Apr 15, 2005
    Replies:
    3
    Views:
    767
    John Gianni
    Apr 27, 2005
  45. Xuefei Bai

    A question about VSS & VDD symbol when CDL in...

    Xuefei Bai, Apr 19, 2005
    Replies:
    2
    Views:
    875
    Andrew Beckett
    Apr 27, 2005
  46. Harryzhu

    How to transfer one foundry's GDSII data to another?

    Harryzhu, Apr 6, 2005
    Replies:
    4
    Views:
    871
    [email protected]
    Apr 27, 2005
  47. Frank Nitsche

    eye diagram (Cadence 4.6)

    Frank Nitsche, Mar 31, 2005
    Replies:
    5
    Views:
    1,063
    John Gianni
    Apr 26, 2005
  48. Kumar

    Tool for Dynamic Logic Synthesis

    Kumar, Apr 26, 2005
    Replies:
    0
    Views:
    744
    Kumar
    Apr 26, 2005
  49. swetha

    How to store results in a Excel file?

    swetha, Mar 24, 2005 ... 2
    Replies:
    23
    Views:
    1,530
    John Gianni
    Apr 26, 2005
  50. cdnlive2005

    Cadence Designer Network - 2005 Call for Papers

    cdnlive2005, Apr 26, 2005
    Replies:
    0
    Views:
    671
    [email protected]
    Apr 26, 2005
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