Cadence

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  1. analogweb

    cdsenv variables

    analogweb, Sep 12, 2006
    Replies:
    4
    Views:
    1,977
    Bernd Fischer
    Sep 13, 2006
  2. v.rod

    what is the difference AMP and protected hdl code?

    v.rod, Sep 13, 2006
    Replies:
    0
    Views:
    760
    v.rod
    Sep 13, 2006
  3. kamesh

    Setting switches for DRC check

    kamesh, Sep 7, 2006
    Replies:
    1
    Views:
    825
    kamesh
    Sep 12, 2006
  4. gmadhavareddy

    regarding model name for schottky diode for AMS cadence

    gmadhavareddy, Sep 11, 2006
    Replies:
    0
    Views:
    1,076
    [email protected]
    Sep 11, 2006
  5. phil

    OCEAN "jobs" grinds to near halt....

    phil, Sep 11, 2006
    Replies:
    0
    Views:
    875
    [email protected]
    Sep 11, 2006
  6. sergio.pesenti

    spectreVerilog Netlisting

    sergio.pesenti, Aug 31, 2006
    Replies:
    1
    Views:
    834
    [email protected]
    Sep 11, 2006
  7. ponderboy

    hwo to migrate a design from a process to another?

    ponderboy, Sep 9, 2006
    Replies:
    1
    Views:
    836
    Jimka
    Sep 9, 2006
  8. xiaofang.chen

    About FormalCheck

    xiaofang.chen, Sep 9, 2006
    Replies:
    0
    Views:
    513
    [email protected]
    Sep 9, 2006
  9. thomas

    Saving subcircuit signals

    thomas, Sep 5, 2006
    Replies:
    2
    Views:
    940
    Andrew Beckett
    Sep 6, 2006
  10. kamesh

    Directing the result from a procedure to a file (with in icfb window).

    kamesh, Sep 3, 2006
    Replies:
    6
    Views:
    754
    Andrew Beckett
    Sep 6, 2006
  11. DReynolds

    Looking for Veriloga lint program

    DReynolds, Aug 24, 2006
    Replies:
    6
    Views:
    778
    Svenn Bjerkem
    Sep 6, 2006
  12. vtcad

    Using geAddHilightFig Function

    vtcad, Sep 5, 2006
    Replies:
    1
    Views:
    1,178
    Suresh Jeevanandam
    Sep 6, 2006
  13. danmc

    assura SVS?

    danmc, Sep 5, 2006
    Replies:
    1
    Views:
    1,050
    [email protected]
    Sep 5, 2006
  14. Poojan Wagh

    device parameters not showing up on devices after simulation annotation

    Poojan Wagh, Sep 5, 2006
    Replies:
    0
    Views:
    872
    Poojan Wagh
    Sep 5, 2006
  15. hdl_book_seller

    Good Verilog reference book: Thomas & Moorby

    hdl_book_seller, Sep 5, 2006
    Replies:
    0
    Views:
    918
    hdl_book_seller
    Sep 5, 2006
  16. Svenn Bjerkem

    spectremdl and measuring in ac

    Svenn Bjerkem, Aug 10, 2006
    Replies:
    14
    Views:
    1,530
    Svenn Bjerkem
    Sep 4, 2006
  17. vic marks

    generated clocks

    vic marks, Sep 2, 2006
    Replies:
    2
    Views:
    666
    arant
    Sep 3, 2006
  18. chinni

    perl

    chinni, Aug 7, 2006
    Replies:
    2
    Views:
    762
    [email protected]
    Sep 3, 2006
  19. John

    Can I skip USR1 & 2 when upgrading from base release to USR3 release?

    John, Aug 19, 2006
    Replies:
    1
    Views:
    989
    [email protected]
    Sep 3, 2006
  20. Thomas Ussmueller

    Spectre 6.0 in IC 5.1.41

    Thomas Ussmueller, Aug 23, 2006
    Replies:
    2
    Views:
    838
    [email protected]
    Sep 3, 2006
  21. n1ist

    length constraints across components

    n1ist, Sep 2, 2006
    Replies:
    0
    Views:
    736
    [email protected]
    Sep 2, 2006
  22. dnshrds

    analog pride

    dnshrds, Aug 30, 2006
    Replies:
    1
    Views:
    518
    [email protected]
    Sep 2, 2006
  23. danmc

    command line dieplot?

    danmc, Aug 24, 2006
    Replies:
    3
    Views:
    562
    danmc
    Sep 1, 2006
  24. Pleasedontreplytoemailaddress

    "if: Expression syntax" error

    Pleasedontreplytoemailaddress, Aug 28, 2006
    Replies:
    6
    Views:
    854
    Pleasedontreplytoemailaddress
    Aug 30, 2006
  25. Tim

    Schematic net highlighting during RCX Parasitic probing

    Tim, Aug 30, 2006
    Replies:
    0
    Views:
    834
    Tim
    Aug 30, 2006
  26. harry

    need skill code to remove the special net in a layout

    harry, Aug 29, 2006
    Replies:
    2
    Views:
    892
    harry
    Aug 30, 2006
  27. DReynolds

    skill for veriloga view copy

    DReynolds, Aug 25, 2006
    Replies:
    2
    Views:
    872
    DReynolds
    Aug 30, 2006
  28. sun_powered

    Can I update directly from a base release to USR3 release?

    sun_powered, Aug 19, 2006
    Replies:
    2
    Views:
    1,119
    Andrew Beckett
    Aug 30, 2006
  29. Allen

    Problem with PNoise

    Allen, Aug 18, 2006
    Replies:
    1
    Views:
    585
    Andrew Beckett
    Aug 30, 2006
  30. vtcad

    Layout Net Tracing

    vtcad, Aug 28, 2006
    Replies:
    2
    Views:
    940
    Andrew Beckett
    Aug 30, 2006
  31. danmc

    setq vs. = vs. arrays

    danmc, Aug 28, 2006
    Replies:
    2
    Views:
    1,109
    danmc
    Aug 29, 2006
  32. cyseok

    device checking in Analog Design Environment

    cyseok, Aug 29, 2006
    Replies:
    0
    Views:
    1,027
    cyseok
    Aug 29, 2006
  33. BtruongCA

    how to extract pad coordinates and names

    BtruongCA, Aug 16, 2006
    Replies:
    5
    Views:
    1,640
    [email protected]
    Aug 29, 2006
  34. anil Kumar

    skill: property of instance in schematic

    anil Kumar, Aug 28, 2006
    Replies:
    1
    Views:
    1,102
    Jimka
    Aug 28, 2006
  35. jean

    LBS

    jean, Aug 23, 2006
    Replies:
    2
    Views:
    907
    jean
    Aug 28, 2006
  36. Davy

    NC-Sim Tcl script tool?

    Davy, Aug 24, 2006
    Replies:
    9
    Views:
    966
    mark anthony
    Aug 28, 2006
  37. Richard

    Integrated output noise using calc ?

    Richard, Aug 27, 2006
    Replies:
    0
    Views:
    644
    Richard
    Aug 27, 2006
  38. Davy

    #$sig , $sig in Cadence NC-Sim Tcl

    Davy, Aug 26, 2006
    Replies:
    1
    Views:
    822
    Frank E. Gennari
    Aug 26, 2006
  39. sajin

    Problem with floating point numbers.

    sajin, Aug 25, 2006
    Replies:
    4
    Views:
    1,204
    Jimka
    Aug 25, 2006
  40. chickenwing2010

    DRC Error Marker Limitation

    chickenwing2010, Aug 25, 2006
    Replies:
    0
    Views:
    951
    [email protected]
    Aug 25, 2006
  41. anil Kumar

    SKILL: How to read a file

    anil Kumar, Aug 21, 2006
    Replies:
    2
    Views:
    7,709
    Jimka
    Aug 23, 2006
  42. Kevin Doherty

    How to find data extents

    Kevin Doherty, Aug 22, 2006
    Replies:
    1
    Views:
    578
    vtcad
    Aug 23, 2006
  43. Chandramohan Neelakantan

    Net name change - problems with Netlisting

    Chandramohan Neelakantan, Aug 18, 2006
    Replies:
    4
    Views:
    669
    Chandramohan Neelakantan
    Aug 23, 2006
  44. danmc

    modify schematic net expressions with skill

    danmc, Aug 23, 2006
    Replies:
    0
    Views:
    882
    danmc
    Aug 23, 2006
  45. stefan.haberla

    Cadence simulation-log problems

    stefan.haberla, Aug 22, 2006
    Replies:
    1
    Views:
    840
    [email protected]
    Aug 22, 2006
  46. Sylvio Triebel

    rodCreateHandle - how to prevent warnings?

    Sylvio Triebel, Jul 14, 2006
    Replies:
    2
    Views:
    1,032
    Sylvio Triebel
    Aug 22, 2006
  47. Bernd Fischer

    Spyware Cleaner

    Bernd Fischer, Aug 18, 2006
    Replies:
    1
    Views:
    946
    Bernd Fischer
    Aug 18, 2006
  48. Pleasedontreplytoemailaddress

    Cadence oscillator simulation problem

    Pleasedontreplytoemailaddress, Aug 14, 2006
    Replies:
    2
    Views:
    1,105
    haran
    Aug 17, 2006
  49. Allen

    How to have the IBM_PDK menu on the layout window

    Allen, Aug 14, 2006
    Replies:
    3
    Views:
    1,071
    Allen
    Aug 17, 2006
  50. ISQED

    Call for Papers - IEEE ISQED07

    ISQED, Aug 16, 2006
    Replies:
    0
    Views:
    778
    ISQED
    Aug 16, 2006
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