Cadence

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  1. ese!

    srcefirst=1

    ese!, Jan 26, 2007
    Replies:
    0
    Views:
    430
    ese!
    Jan 26, 2007
  2. hb_huang

    spectre PSS/Pnoise on Sampling & Hold Circuit

    hb_huang, Jan 17, 2007
    Replies:
    4
    Views:
    1,263
    Andrew Beckett
    Jan 24, 2007
  3. ciranova

    New PyCell Studio release-create PCells that work in Virtuoso and other OpenAccess tools

    ciranova, Jan 24, 2007
    Replies:
    0
    Views:
    1,260
    [email protected]
    Jan 24, 2007
  4. sm

    Need help with dleteing all TEXT, CIRCLES, LINES from one "class/sub class" in Allegro

    sm, Jan 23, 2007
    Replies:
    0
    Views:
    821
    sm
    Jan 23, 2007
  5. nd_electro

    Distributed Processing with VSdE in LBS_DEFAULT mode

    nd_electro, Jan 23, 2007
    Replies:
    0
    Views:
    1,004
    nd_electro
    Jan 23, 2007
  6. satya

    SKILL FFI

    satya, Jan 5, 2007
    Replies:
    3
    Views:
    510
    Jimka
    Jan 22, 2007
  7. snau-ktv

    Monte Carlo and highly matched structures

    snau-ktv, Jan 18, 2007
    Replies:
    1
    Views:
    795
    S. Badel
    Jan 19, 2007
  8. wilcn

    About the test access insertion selectively to the PCB with Allegro.

    wilcn, Jan 19, 2007
    Replies:
    0
    Views:
    741
    wilcn
    Jan 19, 2007
  9. blond

    XF analysis in OCEAN

    blond, Jan 18, 2007
    Replies:
    0
    Views:
    826
    [email protected]
    Jan 18, 2007
  10. kev

    simulating 3rd party standard lib cells

    kev, Nov 13, 2006
    Replies:
    13
    Views:
    1,236
    Svenn Are Bjerkem
    Jan 18, 2007
  11. ankur101

    Inconsistencies in hpiceS netlist extraction in ADE

    ankur101, Jan 16, 2007
    Replies:
    1
    Views:
    789
    Andrew Beckett
    Jan 18, 2007
  12. Hugo Franca

    Virtuoso Schematic Editor: Sheet border size, titles, etc

    Hugo Franca, Jan 12, 2007
    Replies:
    3
    Views:
    1,049
    [email protected]
    Jan 17, 2007
  13. wolfpack307

    Some question on SKILL

    wolfpack307, Dec 16, 2006
    Replies:
    3
    Views:
    455
    vlsidesign
    Jan 16, 2007
  14. Kuan Zhou

    Cadence Setup Problem in Fedora 6

    Kuan Zhou, Jan 15, 2007
    Replies:
    2
    Views:
    652
    satya
    Jan 16, 2007
  15. linkin

    modulo operation in calculator?

    linkin, Jan 15, 2007
    Replies:
    1
    Views:
    1,100
    linkin
    Jan 15, 2007
  16. Gang Bu

    How to simulate PLL phase noise efficiently

    Gang Bu, Jan 9, 2007
    Replies:
    1
    Views:
    950
    Andrew Beckett
    Jan 12, 2007
  17. camelot

    parasitic extraction question

    camelot, Jan 12, 2007
    Replies:
    0
    Views:
    715
    camelot
    Jan 12, 2007
  18. Shenli

    Pass string to $system in SystemVerilog?

    Shenli, Jan 12, 2007
    Replies:
    1
    Views:
    852
    [email protected]
    Jan 12, 2007
  19. anil Kumar

    how to change CDF parameter value

    anil Kumar, Jan 12, 2007
    Replies:
    0
    Views:
    1,440
    anil Kumar
    Jan 12, 2007
  20. Shenli

    Call Perl in Verilog or SV?

    Shenli, Jan 11, 2007
    Replies:
    2
    Views:
    968
    Alex
    Jan 11, 2007
  21. ajin

    CDF parameter display problem

    ajin, Nov 8, 2006
    Replies:
    12
    Views:
    1,387
    kev
    Jan 11, 2007
  22. petrubac

    bsource, fmod and $time compatibility problem?

    petrubac, Jan 10, 2007
    Replies:
    2
    Views:
    807
    Petru
    Jan 11, 2007
  23. Svenn Are Bjerkem

    Controlling the zoom factor used by hiZoomInAtMouse

    Svenn Are Bjerkem, Jan 10, 2007
    Replies:
    2
    Views:
    695
    Pete nospam Zakel
    Jan 11, 2007
  24. Raghavendra

    IC5033/Assura on Linux do not release memory.

    Raghavendra, Dec 21, 2006
    Replies:
    4
    Views:
    871
    Tim
    Jan 10, 2007
  25. Jan Mikkelsen

    ASSURA - failed to build VDB

    Jan Mikkelsen, Jan 10, 2007
    Replies:
    0
    Views:
    3,487
    Jan Mikkelsen
    Jan 10, 2007
  26. kev

    linking cdf params and spectre netlist

    kev, Jan 10, 2007
    Replies:
    1
    Views:
    839
    kev
    Jan 10, 2007
  27. Davy

    uRM task-level interface?

    Davy, Jan 10, 2007
    Replies:
    0
    Views:
    506
    Davy
    Jan 10, 2007
  28. sm

    Adding CLASS & SUBCLASS to Allegro database using skill

    sm, Jan 10, 2007
    Replies:
    0
    Views:
    3,237
    sm
    Jan 10, 2007
  29. ajd

    How to control what parameters are displayed during DC Operating Point back-annotation?

    ajd, Dec 14, 2006
    Replies:
    3
    Views:
    1,250
    ctxuser
    Jan 9, 2007
  30. greendays_01

    Veriloga

    greendays_01, Jan 3, 2007
    Replies:
    1
    Views:
    480
    Andrew Beckett
    Jan 9, 2007
  31. sm

    SKILL code for file selection GUI

    sm, Dec 22, 2006
    Replies:
    2
    Views:
    1,226
    Andrew Beckett
    Jan 9, 2007
  32. Erik Wanta

    convert SKILL list to string

    Erik Wanta, Dec 18, 2006
    Replies:
    8
    Views:
    7,962
    Andrew Beckett
    Jan 9, 2007
  33. manjunath

    via doubling

    manjunath, Dec 11, 2006
    Replies:
    3
    Views:
    525
    Andrew Beckett
    Jan 9, 2007
  34. us1710

    problem in monte carlo analysis

    us1710, Dec 8, 2006
    Replies:
    1
    Views:
    990
    Andrew Beckett
    Jan 9, 2007
  35. oliver

    spectre pnoise / timedomain - unexpected results

    oliver, Dec 3, 2006
    Replies:
    1
    Views:
    1,093
    Andrew Beckett
    Jan 9, 2007
  36. vlsidesign

    newbie question on using optional in procedures

    vlsidesign, Jan 3, 2007
    Replies:
    5
    Views:
    971
    Suresh Jeevanandam
    Jan 5, 2007
  37. medha.kulkarni

    dbGetTrueOverlaps

    medha.kulkarni, Dec 29, 2006
    Replies:
    4
    Views:
    863
    Jimka
    Jan 1, 2007
  38. blond

    distributed simulation: ksh problem

    blond, Dec 28, 2006
    Replies:
    2
    Views:
    691
    [email protected]
    Dec 30, 2006
  39. vdauthor

    Visual IP Designer interresting new EDA tool/Automatic VHDL Generation

    vdauthor, Dec 29, 2006
    Replies:
    0
    Views:
    851
    vdauthor
    Dec 29, 2006
  40. supra

    schematic to layout

    supra, Dec 15, 2006
    Replies:
    1
    Views:
    489
    Suresh Jeevanandam
    Dec 27, 2006
  41. sajin

    doubt regarding polygon layers

    sajin, Dec 22, 2006
    Replies:
    2
    Views:
    713
    sajin
    Dec 26, 2006
  42. Thomas Ussmueller

    Problems setting up Allegro

    Thomas Ussmueller, Nov 17, 2006
    Replies:
    2
    Views:
    622
    [email protected]
    Dec 21, 2006
  43. Mohan R

    Assura RCX extraction with shorts ?

    Mohan R, Dec 20, 2006
    Replies:
    0
    Views:
    797
    Mohan R
    Dec 20, 2006
  44. jowong1

    VHDLIn in Cadence

    jowong1, Dec 18, 2006
    Replies:
    0
    Views:
    509
    [email protected]
    Dec 18, 2006
  45. yudi

    How to snap instances and shapes from grid 0.1 to 0.0625

    yudi, Dec 13, 2006
    Replies:
    1
    Views:
    1,175
    Erik Wanta
    Dec 18, 2006
  46. wzhenning

    Export layout from Encounter to VLE

    wzhenning, Dec 11, 2006
    Replies:
    17
    Views:
    1,136
    [email protected]
    Dec 18, 2006
  47. us1710

    problem in monte carlo analysis for large runs

    us1710, Dec 18, 2006
    Replies:
    0
    Views:
    859
    [email protected]
    Dec 18, 2006
  48. Norman

    plot Transient voltage of internal BVIC nodes in spectre

    Norman, Dec 15, 2006
    Replies:
    1
    Views:
    916
    wolf6873
    Dec 17, 2006
  49. vlsidesign

    using leSearchHierarchy with brackets

    vlsidesign, Dec 16, 2006
    Replies:
    1
    Views:
    630
    vlsidesign
    Dec 17, 2006
  50. rachelms79

    veriloga analog bus sample?

    rachelms79, Dec 13, 2006
    Replies:
    2
    Views:
    691
    DReynolds
    Dec 15, 2006
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