Cadence

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  1. ponderboy

    netlist error

    ponderboy, Feb 26, 2007
    Replies:
    0
    Views:
    990
    ponderboy
    Feb 26, 2007
  2. sheikhmo

    Finding power and operating point in Spectre WITHOUT ADE

    sheikhmo, Feb 22, 2007
    Replies:
    1
    Views:
    883
    Andrew Beckett
    Feb 26, 2007
  3. vlasinvlad

    fflush(stdout) for SKILL

    vlasinvlad, Feb 26, 2007
    Replies:
    1
    Views:
    970
    Suresh Jeevanandam
    Feb 26, 2007
  4. wzhenning

    encounter problems

    wzhenning, Feb 23, 2007
    Replies:
    3
    Views:
    604
    [email protected]
    Feb 23, 2007
  5. Tim

    Create schematic from RCX extrated view

    Tim, Feb 22, 2007
    Replies:
    4
    Views:
    698
    S.Badel
    Feb 23, 2007
  6. sarathcvk

    Creating lists using OCEAN

    sarathcvk, Feb 21, 2007
    Replies:
    2
    Views:
    660
    [email protected]
    Feb 22, 2007
  7. LindaM

    Spectre question needs answer on cdnusers.org

    LindaM, Feb 21, 2007
    Replies:
    0
    Views:
    817
    LindaM
    Feb 21, 2007
  8. kovalcik

    External applications within Cadence

    kovalcik, Feb 20, 2007
    Replies:
    1
    Views:
    834
    [email protected]
    Feb 20, 2007
  9. Svenn Are Bjerkem

    How to set the default path for new libraries in the library manager?

    Svenn Are Bjerkem, Feb 20, 2007
    Replies:
    0
    Views:
    848
    Svenn Are Bjerkem
    Feb 20, 2007
  10. atul.ee

    PSS Convergence Issue

    atul.ee, Feb 20, 2007
    Replies:
    0
    Views:
    1,293
    [email protected]
    Feb 20, 2007
  11. EEngineer

    Cadence synthesis tool from VHDL to netlist?

    EEngineer, Feb 16, 2007
    Replies:
    3
    Views:
    957
    Andrew Beckett
    Feb 20, 2007
  12. Ash

    skill:change drc error marker to metal layer

    Ash, Jan 10, 2007
    Replies:
    1
    Views:
    1,113
    [email protected]
    Feb 20, 2007
  13. nvss

    Need help in linear scaling of standard cell layout from 130nm to 90mn

    nvss, Jan 29, 2007
    Replies:
    2
    Views:
    997
    [email protected]
    Feb 20, 2007
  14. fritz.karl

    Is there anyway to compare two GDS files layer by layer?

    fritz.karl, Jan 31, 2007
    Replies:
    4
    Views:
    1,174
    [email protected]
    Feb 20, 2007
  15. nimayshah

    Extracting wire parasitic from silicon ensemble or other tool

    nimayshah, Feb 13, 2007
    Replies:
    1
    Views:
    735
    [email protected]
    Feb 20, 2007
  16. llipschutz

    Width calculation

    llipschutz, Feb 12, 2007
    Replies:
    2
    Views:
    712
    [email protected]
    Feb 20, 2007
  17. Suresh Jeevanandam

    cadence wiki

    Suresh Jeevanandam, Feb 17, 2007
    Replies:
    1
    Views:
    907
    Suresh Jeevanandam
    Feb 19, 2007
  18. Reotaro Hashemoto

    IC-Station-like strokes definition in Virtuoso

    Reotaro Hashemoto, Feb 16, 2007
    Replies:
    3
    Views:
    850
    Reotaro Hashemoto
    Feb 18, 2007
  19. wantcar

    Encounter Questions

    wantcar, Feb 10, 2007
    Replies:
    4
    Views:
    543
    [email protected]
    Feb 16, 2007
  20. Reotaro Hashemoto

    Where's my .cdsinit ???

    Reotaro Hashemoto, Feb 14, 2007
    Replies:
    13
    Views:
    2,135
    Svenn Are Bjerkem
    Feb 16, 2007
  21. Reotaro Hashemoto

    About SKILL ~> and -> Operators

    Reotaro Hashemoto, Feb 14, 2007
    Replies:
    6
    Views:
    1,331
    Andrew Beckett
    Feb 16, 2007
  22. vlsidesign

    using a port in sub-procedure

    vlsidesign, Feb 16, 2007
    Replies:
    0
    Views:
    638
    vlsidesign
    Feb 16, 2007
  23. rh0dium

    CAD Engineer Wanted!! - Someone with a brain please apply..

    rh0dium, Feb 14, 2007
    Replies:
    0
    Views:
    736
    rh0dium
    Feb 14, 2007
  24. sc

    get CIW options from skill code

    sc, Feb 13, 2007
    Replies:
    0
    Views:
    974
    sc
    Feb 13, 2007
  25. vlasinvlad

    SKILL database object question

    vlasinvlad, Feb 13, 2007
    Replies:
    1
    Views:
    764
    Suresh Jeevanandam
    Feb 13, 2007
  26. danniel

    running simulation is very slow

    danniel, Feb 12, 2007
    Replies:
    3
    Views:
    735
    Svenn Are Bjerkem
    Feb 13, 2007
  27. ahmad.abdulghany

    required SKILL code to automate simulations

    ahmad.abdulghany, Feb 6, 2007
    Replies:
    5
    Views:
    914
    Reotaro Hashemoto
    Feb 13, 2007
  28. MS_ASIC_LOVER

    Cadence Virtuoso ADE - Simulation and Plotting Help!

    MS_ASIC_LOVER, Feb 7, 2007
    Replies:
    2
    Views:
    922
    S. Badel
    Feb 13, 2007
  29. SS

    64 bit linux and 64 bit icfb executable

    SS, Feb 12, 2007
    Replies:
    2
    Views:
    1,237
    SS
    Feb 12, 2007
  30. Verictor

    How to use a DEF in SoC Encounter

    Verictor, Jan 30, 2007
    Replies:
    7
    Views:
    864
    Verictor
    Feb 12, 2007
  31. MS_ASIC_LOVER

    Displaying parameter of internal component to the top-level block

    MS_ASIC_LOVER, Feb 10, 2007
    Replies:
    1
    Views:
    1,138
    Svenn Are Bjerkem
    Feb 12, 2007
  32. Reotaro Hashemoto

    Unkown icfb startup problem!! :(

    Reotaro Hashemoto, Feb 11, 2007
    Replies:
    1
    Views:
    752
    Reotaro Hashemoto
    Feb 12, 2007
  33. jm.suresh

    gvim: doc string editing

    jm.suresh, Feb 11, 2007
    Replies:
    0
    Views:
    612
    [email protected]
    Feb 11, 2007
  34. MS_ASIC_LOVER

    Cadence back-end! urgent help please!! :(

    MS_ASIC_LOVER, Feb 7, 2007
    Replies:
    2
    Views:
    801
    [email protected]
    Feb 9, 2007
  35. jutek

    layout view

    jutek, Feb 8, 2007
    Replies:
    1
    Views:
    437
    [email protected]
    Feb 9, 2007
  36. Golana Rengised

    "Rapid IP3" and other specialized analyses

    Golana Rengised, Feb 8, 2007
    Replies:
    0
    Views:
    799
    Golana Rengised
    Feb 8, 2007
  37. vlsidesign

    instPin is nil

    vlsidesign, Jan 9, 2007
    Replies:
    6
    Views:
    573
    Suresh Jeevanandam
    Feb 8, 2007
  38. Farhaan

    Generic differential design routing with CCAR

    Farhaan, Feb 6, 2007
    Replies:
    2
    Views:
    824
    Farhaan
    Feb 7, 2007
  39. Verictor

    gate-level simulation problem

    Verictor, Feb 6, 2007
    Replies:
    0
    Views:
    1,464
    Verictor
    Feb 6, 2007
  40. maddy

    calibre DRC/LVS flow

    maddy, Feb 1, 2007
    Replies:
    3
    Views:
    1,146
    maddy
    Feb 5, 2007
  41. spectrallypure

    Make LMHOSTID to output MAC in "UNIX format" when ran in linux

    spectrallypure, Feb 3, 2007
    Replies:
    3
    Views:
    1,192
    [email protected]
    Feb 4, 2007
  42. anil Kumar

    copying schematic of many cells in one cell

    anil Kumar, Jan 25, 2007
    Replies:
    2
    Views:
    952
    vlsidesign
    Feb 3, 2007
  43. vlsidesign

    re-attaching library to different tech lib

    vlsidesign, Feb 1, 2007
    Replies:
    2
    Views:
    1,708
    vlsidesign
    Feb 2, 2007
  44. unfrostedpoptart

    ncsim -exit question

    unfrostedpoptart, Feb 2, 2007
    Replies:
    0
    Views:
    882
    unfrostedpoptart
    Feb 2, 2007
  45. amnon

    Removing the W,L,nf,m from Transistor in Schematics

    amnon, Feb 1, 2007
    Replies:
    1
    Views:
    581
    Andy
    Feb 1, 2007
  46. danmc

    adding connectivity to metal

    danmc, Jan 30, 2007
    Replies:
    2
    Views:
    596
    Tim
    Jan 31, 2007
  47. Marius C.

    Cadence, stupid question

    Marius C., Jan 24, 2007
    Replies:
    3
    Views:
    942
    Edward Kalenda
    Jan 29, 2007
  48. svilen

    schematic - layout

    svilen, Jan 26, 2007
    Replies:
    4
    Views:
    500
    [email protected]
    Jan 29, 2007
  49. kev

    skill copy cellview

    kev, Jan 25, 2007
    Replies:
    3
    Views:
    2,095
    kev
    Jan 29, 2007
  50. Tim

    VXL placing cells/pcells off grid

    Tim, Jan 10, 2007
    Replies:
    5
    Views:
    847
    vlsidesign
    Jan 26, 2007
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