Cadence

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  1. Paul Shepherd

    Netlisting resistors and capacitors through HNL for hspice?

    Paul Shepherd, Sep 9, 2011
    Replies:
    2
    Views:
    1,357
    Andrew Beckett
    Sep 26, 2011
  2. jren

    precision of float

    jren, Sep 6, 2011
    Replies:
    3
    Views:
    1,262
    Andrew Beckett
    Sep 26, 2011
  3. vivek

    Avoid encounter from inserting buffer in a net by breaking the connection.

    vivek, Sep 21, 2011
    Replies:
    0
    Views:
    994
    vivek
    Sep 21, 2011
  4. jmss

    ADE vs OSS netlisting

    jmss, Aug 25, 2011
    Replies:
    2
    Views:
    1,648
    jmss
    Sep 19, 2011
  5. jren

    stretch handle accessed by parent cell

    jren, Sep 14, 2011
    Replies:
    0
    Views:
    1,104
    jren
    Sep 14, 2011
  6. Poojan Wagh

    UWI format and branches, attributes

    Poojan Wagh, Sep 12, 2011
    Replies:
    1
    Views:
    1,115
    Poojan Wagh
    Sep 12, 2011
  7. PolyPusher

    Using Skill to change properties on fets..

    PolyPusher, Aug 31, 2011
    Replies:
    3
    Views:
    1,802
    PolyPusher
    Sep 6, 2011
  8. sg

    Shorted signals

    sg, Aug 29, 2011
    Replies:
    1
    Views:
    1,034
    sg
    Aug 29, 2011
  9. bsrin

    CIW banner labels are missing

    bsrin, Aug 19, 2011
    Replies:
    1
    Views:
    1,120
    Pete Z.
    Aug 25, 2011
  10. jren

    cdf lost every time I log out from cadence

    jren, Aug 25, 2011
    Replies:
    4
    Views:
    1,252
    jren
    Aug 25, 2011
  11. Rick Mattern

    simulation is still running but the ade-xl believes it has finished

    Rick Mattern, Aug 15, 2011
    Replies:
    0
    Views:
    953
    Rick Mattern
    Aug 15, 2011
  12. Rene

    VHDL import error message

    Rene, Aug 12, 2011
    Replies:
    0
    Views:
    1,028
    Rene
    Aug 12, 2011
  13. sg_vlsi

    Reg:Change via property in IC613

    sg_vlsi, Aug 8, 2011
    Replies:
    3
    Views:
    1,069
    Andrew Beckett
    Aug 12, 2011
  14. Hannes

    Use of compare_model_timing in SoC Encounter

    Hannes, Aug 10, 2011
    Replies:
    0
    Views:
    873
    Hannes
    Aug 10, 2011
  15. KLARO

    Allegro expand flag ?

    KLARO, Aug 8, 2011
    Replies:
    0
    Views:
    1,009
    KLARO
    Aug 8, 2011
  16. I-F AB

    SKILL command: setof , exists

    I-F AB, Jul 28, 2011
    Replies:
    2
    Views:
    1,217
    I-F AB
    Aug 3, 2011
  17. Dennis Blau

    velocity: multiple identical partitions

    Dennis Blau, Aug 1, 2011
    Replies:
    1
    Views:
    965
    Dennis Blau
    Aug 2, 2011
  18. pforPDK

    what are good checks to verify applied CDF on a device symbol in schematic

    pforPDK, Jun 15, 2011
    Replies:
    1
    Views:
    953
    I-F AB
    Aug 1, 2011
  19. Rick Mattern

    skill to access ADEXL options

    Rick Mattern, Jul 28, 2011
    Replies:
    0
    Views:
    1,022
    Rick Mattern
    Jul 28, 2011
  20. I-F AB

    SKILL command: setof , exists

    I-F AB, Jul 28, 2011
    Replies:
    0
    Views:
    2,390
    I-F AB
    Jul 28, 2011
  21. Rick Mattern

    skill syntax question

    Rick Mattern, Jul 22, 2011
    Replies:
    1
    Views:
    904
    Marcel Preda
    Jul 24, 2011
  22. sg

    string 2 list

    sg, Jul 10, 2011
    Replies:
    2
    Views:
    912
    Pete Z.
    Jul 19, 2011
  23. Konx

    Cadence Encounter: set the cell orientation

    Konx, Jul 12, 2011
    Replies:
    0
    Views:
    1,071
    Konx
    Jul 12, 2011
  24. David Kubalek

    Crash during loading of large (~3GB) av_extracted file

    David Kubalek, Jul 4, 2011
    Replies:
    2
    Views:
    861
    Andrew Beckett
    Jul 5, 2011
  25. murtuza shariff

    Subject : LinkedIn Event: Web Application Conference

    murtuza shariff, Jul 2, 2011
    Replies:
    0
    Views:
    953
    murtuza shariff
    Jul 2, 2011
  26. aero

    Segmentation fault on solaris 10 sparc

    aero, Jun 28, 2011
    Replies:
    1
    Views:
    1,508
    Andrew Beckett
    Jul 1, 2011
  27. FraNi

    noise analysis in IC61

    FraNi, Jun 21, 2011
    Replies:
    1
    Views:
    993
    Sohaib Saadat Afridi
    Jun 22, 2011
  28. Konx

    RTL Compiler: loading of "schematics"

    Konx, Jun 17, 2011
    Replies:
    0
    Views:
    982
    Konx
    Jun 17, 2011
  29. Marcel Preda

    merge all shapes on a specific layer

    Marcel Preda, Jun 8, 2011
    Replies:
    1
    Views:
    1,541
    Andrew Beckett
    Jun 9, 2011
  30. Paul Shepherd

    Displaying CDF parameter based on cell type?

    Paul Shepherd, May 26, 2011
    Replies:
    2
    Views:
    1,090
    Paul Shepherd
    Jun 7, 2011
  31. Marcel Preda

    dbCreateProp , and type have to be a dbObjId

    Marcel Preda, May 25, 2011
    Replies:
    5
    Views:
    1,581
    Marcel Preda
    Jun 3, 2011
  32. Tarek

    RHEL6 support?

    Tarek, May 20, 2011
    Replies:
    1
    Views:
    1,125
    Andrew Beckett
    Jun 1, 2011
  33. Rick Mattern

    voltage storm filtering presistors

    Rick Mattern, May 24, 2011
    Replies:
    0
    Views:
    989
    Rick Mattern
    May 24, 2011
  34. leo1408

    Invalid dev or device instance in dc analysis

    leo1408, May 21, 2011
    Replies:
    0
    Views:
    1,031
    leo1408
    May 21, 2011
  35. Sam

    PZ Analysis on Verilog A Model

    Sam, May 4, 2011
    Replies:
    1
    Views:
    959
    Kenneth Brun Nielsen
    May 20, 2011
  36. zhouk01

    adding XA in analog artist

    zhouk01, May 20, 2011
    Replies:
    0
    Views:
    918
    zhouk01
    May 20, 2011
  37. GS

    bbox of instance in schematic

    GS, May 18, 2011
    Replies:
    1
    Views:
    1,088
    Marcel Preda
    May 19, 2011
  38. Debjit Pal

    Unable to create parallel thread of execution with fork join

    Debjit Pal, May 9, 2011
    Replies:
    0
    Views:
    1,075
    Debjit Pal
    May 9, 2011
  39. Gio

    errset command question

    Gio, May 7, 2011
    Replies:
    1
    Views:
    1,014
    Andrew Beckett
    May 8, 2011
  40. Sam

    Noise Analysis

    Sam, Apr 30, 2011
    Replies:
    0
    Views:
    996
    Sam
    Apr 30, 2011
  41. EDPHWSW

    Spicy Schematics for iPad

    EDPHWSW, Apr 29, 2011
    Replies:
    0
    Views:
    1,023
    EDPHWSW
    Apr 29, 2011
  42. mvalery

    Connectivity Mark Net for temporary layers

    mvalery, Apr 27, 2011
    Replies:
    0
    Views:
    1,053
    mvalery
    Apr 27, 2011
  43. analogIC

    PoleZero VS. AC analysis in Spectre

    analogIC, Apr 19, 2011
    Replies:
    1
    Views:
    1,218
    Andrew Beckett
    Apr 22, 2011
  44. Nilay

    'freq' parameter in ac analysis

    Nilay, Apr 20, 2011
    Replies:
    1
    Views:
    1,056
    Andrew Beckett
    Apr 22, 2011
  45. fitz

    A. G. Lisi's E8 model may be showing us what both our space & timereally are.

    fitz, Apr 20, 2011
    Replies:
    0
    Views:
    929
    fitz
    Apr 20, 2011
  46. Hannes

    Problems with pin assignment file in Encounter Test

    Hannes, Apr 18, 2011
    Replies:
    0
    Views:
    972
    Hannes
    Apr 18, 2011
  47. Qian.Shun

    Is there a way to add outputs/expressions into artist automatically?

    Qian.Shun, Apr 15, 2011
    Replies:
    0
    Views:
    896
    [email protected]
    Apr 15, 2011
  48. sg

    dbCreateNet using itkDB

    sg, Mar 24, 2011
    Replies:
    1
    Views:
    1,004
    Andrew Beckett
    Apr 13, 2011
  49. RC MURALI

    Not Getting "Select Via Layers for Mark Net" form while doing Mark Net

    RC MURALI, Apr 6, 2011
    Replies:
    1
    Views:
    1,120
    Andrew Beckett
    Apr 13, 2011
  50. RC MURALI

    Mapping of one CellView to another in Cadence Layout XL Gen. From Source

    RC MURALI, Apr 1, 2011
    Replies:
    2
    Views:
    1,081
    RC MURALI
    Apr 6, 2011
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