Cadence

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  1. eric.d.fitzsimmons

    Path command

    eric.d.fitzsimmons, Feb 19, 2009
    Replies:
    4
    Views:
    686
    [email protected]
    Feb 24, 2009
  2. JD

    section definition in Spectre

    JD, Feb 23, 2009
    Replies:
    1
    Views:
    626
    Andrew Beckett
    Feb 24, 2009
  3. nicollete

    spectre and ic5141

    nicollete, Feb 20, 2009
    Replies:
    1
    Views:
    703
    Andrew Beckett
    Feb 21, 2009
  4. Anuj

    SKILL file to read a list of cell to work on

    Anuj, Feb 20, 2009
    Replies:
    1
    Views:
    871
    Andrew Beckett
    Feb 20, 2009
  5. I-F AB

    layer rules class in Virtuoso techfile

    I-F AB, Feb 19, 2009
    Replies:
    2
    Views:
    910
    I-F AB
    Feb 20, 2009
  6. Govind Kulkarni

    Cadence stream-In layermap

    Govind Kulkarni, Feb 16, 2009
    Replies:
    7
    Views:
    1,030
    Andrew Beckett
    Feb 19, 2009
  7. SS

    reading an skill file and storing it in a list

    SS, Feb 19, 2009
    Replies:
    1
    Views:
    743
    Rajes
    Feb 19, 2009
  8. Tao Chen

    How to reduce the size of the postscript file generated by virtuoso6.1

    Tao Chen, Feb 19, 2009
    Replies:
    0
    Views:
    1,008
    Tao Chen
    Feb 19, 2009
  9. Sunil_rpine

    How to avoid implicit netlisting in AMS simulator

    Sunil_rpine, Feb 18, 2009
    Replies:
    0
    Views:
    908
    Sunil_rpine
    Feb 18, 2009
  10. Adam

    Assura LVS question

    Adam, Feb 10, 2009
    Replies:
    5
    Views:
    1,434
    Adam
    Feb 17, 2009
  11. Sunil_rpine

    resolving instance bindings in AMS

    Sunil_rpine, Feb 14, 2009
    Replies:
    2
    Views:
    686
    Sunil_rpine
    Feb 16, 2009
  12. Tony

    set the parameters of the fourier component from analogLib

    Tony, Feb 9, 2009
    Replies:
    4
    Views:
    1,075
    Tony
    Feb 13, 2009
  13. spectrallypure

    One .cdsenv, several design kits...

    spectrallypure, Feb 5, 2009
    Replies:
    5
    Views:
    1,140
    Andrew Beckett
    Feb 12, 2009
  14. Vaibhav

    Cadence Screen Updates/Refresh terribly slow

    Vaibhav, Feb 12, 2009
    Replies:
    0
    Views:
    981
    Vaibhav
    Feb 12, 2009
  15. layoutDesign

    XL needs to open schematic for Edit to extract connectivity

    layoutDesign, Feb 4, 2009
    Replies:
    2
    Views:
    745
    Tim
    Feb 12, 2009
  16. Evel

    move a symbol function“axlTransformObject”

    Evel, Feb 12, 2009
    Replies:
    1
    Views:
    886
    Andrew Beckett
    Feb 12, 2009
  17. Awqati

    Commercial Products with Cadence

    Awqati, Feb 11, 2009
    Replies:
    1
    Views:
    597
    Andrew Beckett
    Feb 12, 2009
  18. Tarek

    does icfb save $PWD when its launched?

    Tarek, Feb 9, 2009
    Replies:
    3
    Views:
    700
    Nicolas
    Feb 11, 2009
  19. Adam

    Difference between Virtuoso_QRC_Extraction_GXL andVirtuoso_QRC_Extraction_XL?

    Adam, Feb 6, 2009
    Replies:
    6
    Views:
    550
    Adam
    Feb 10, 2009
  20. Roger Light

    cdb2oa error

    Roger Light, Jan 29, 2009
    Replies:
    2
    Views:
    925
    Roger Light
    Feb 10, 2009
  21. Reotaro Hashemoto

    Can Assura LVS rules be included within drcExtractRules() function?

    Reotaro Hashemoto, Feb 9, 2009
    Replies:
    2
    Views:
    1,081
    Reotaro Hashemoto
    Feb 9, 2009
  22. Lakshman

    Manual routing in Cadance

    Lakshman, Dec 14, 2008
    Replies:
    6
    Views:
    920
    Andrew Beckett
    Feb 9, 2009
  23. sudhasubramaniam

    changing pathwidth while using "enterPath" funtion

    sudhasubramaniam, Feb 5, 2009
    Replies:
    6
    Views:
    678
    Andrew Beckett
    Feb 9, 2009
  24. Sunil_rpine

    problem with running AMS

    Sunil_rpine, Feb 6, 2009
    Replies:
    2
    Views:
    574
    Sunil_rpine
    Feb 9, 2009
  25. Taimur

    SystemVerilog with AMS?

    Taimur, Feb 6, 2009
    Replies:
    1
    Views:
    818
    Riad KACED
    Feb 8, 2009
  26. Adam

    Error when importing GDS file

    Adam, Feb 5, 2009
    Replies:
    7
    Views:
    828
    Adam
    Feb 6, 2009
  27. Mobil

    How to make verilogA work?

    Mobil, Feb 4, 2009
    Replies:
    2
    Views:
    663
    Mobil
    Feb 6, 2009
  28. layoutDesign

    efficiently handling of flat data in skill

    layoutDesign, Feb 5, 2009
    Replies:
    3
    Views:
    754
    gary
    Feb 6, 2009
  29. Adam

    Mismatched device problem of Assura LVS

    Adam, Feb 3, 2009
    Replies:
    1
    Views:
    959
    layoutDesign
    Feb 5, 2009
  30. spectrallypure

    Error with jre when loading corners tool

    spectrallypure, Feb 3, 2009
    Replies:
    4
    Views:
    886
    spectrallypure
    Feb 4, 2009
  31. erikwanta

    get instance terminals to print as pins in AMS

    erikwanta, Feb 1, 2009
    Replies:
    1
    Views:
    725
    Andrew Beckett
    Feb 4, 2009
  32. crazyjoe2009

    I have a question about PDK integrity

    crazyjoe2009, Feb 2, 2009
    Replies:
    6
    Views:
    724
    Andrew Beckett
    Feb 4, 2009
  33. mm77

    Leakage currents & mismatch

    mm77, Feb 2, 2009
    Replies:
    4
    Views:
    840
    erikl
    Feb 3, 2009
  34. layoutDesign

    connectivity problem

    layoutDesign, Jan 31, 2009
    Replies:
    4
    Views:
    502
    layoutDesign
    Feb 2, 2009
  35. crazyjoe2009

    What is cdsParams(1,2,...) ???

    crazyjoe2009, Feb 2, 2009
    Replies:
    1
    Views:
    599
    Andrew Beckett
    Feb 2, 2009
  36. analogsuperninja

    SKILL language predefined globals

    analogsuperninja, Jan 31, 2009
    Replies:
    1
    Views:
    740
    erikwanta
    Feb 1, 2009
  37. Kumar

    How to create a LEF file from GDS?.

    Kumar, Jan 30, 2009
    Replies:
    1
    Views:
    1,291
    Marc Heise
    Jan 30, 2009
  38. vishwabr.gowda

    need help

    vishwabr.gowda, Jan 29, 2009
    Replies:
    2
    Views:
    502
    Andrew Beckett
    Jan 29, 2009
  39. get2vsp

    Strange warning in 'pnoise' simulations with IC613(ADE-XL) andMMSIM70

    get2vsp, Jan 29, 2009
    Replies:
    0
    Views:
    1,026
    [email protected]
    Jan 29, 2009
  40. VP

    Problem in setting up Analog Design Environment - XL/GXL in IC613

    VP, Jan 26, 2009
    Replies:
    1
    Views:
    1,024
    Andrew Beckett
    Jan 27, 2009
  41. Reotaro Hashemoto

    Is it possible to control cell names in GDS during streamout?

    Reotaro Hashemoto, Jan 26, 2009
    Replies:
    1
    Views:
    898
    Andrew Beckett
    Jan 27, 2009
  42. Jan

    cadence ic5141

    Jan, Jan 26, 2009
    Replies:
    1
    Views:
    1,416
    Andrew Beckett
    Jan 27, 2009
  43. ecnedad

    Process Table exhausted

    ecnedad, Jan 26, 2009
    Replies:
    3
    Views:
    540
    Andrew Beckett
    Jan 27, 2009
  44. ecnedad

    Freezing problem on other Linux machine

    ecnedad, Jan 18, 2009
    Replies:
    3
    Views:
    752
    fogh
    Jan 27, 2009
  45. layoutDesign

    delete figure of the pin, what else is needed for cleanup

    layoutDesign, Jan 24, 2009
    Replies:
    1
    Views:
    769
    Riad KACED
    Jan 26, 2009
  46. SS

    Placing Virtuoso Data using SoC Encounter

    SS, Jan 25, 2009
    Replies:
    0
    Views:
    677
    SS
    Jan 25, 2009
  47. eric.d.fitzsimmons

    Via Doubler

    eric.d.fitzsimmons, Jan 16, 2009
    Replies:
    6
    Views:
    566
    Andrew Beckett
    Jan 21, 2009
  48. Adam

    Assura DRC problem of Guard ring

    Adam, Jan 20, 2009
    Replies:
    1
    Views:
    1,009
    Andrew Beckett
    Jan 20, 2009
  49. SS

    moving via pcells to the topmost level

    SS, Dec 5, 2008
    Replies:
    4
    Views:
    861
    SS
    Jan 19, 2009
  50. eric.d.fitzsimmons

    Via Doubler

    eric.d.fitzsimmons, Jan 16, 2009
    Replies:
    0
    Views:
    524
    [email protected]
    Jan 16, 2009
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